
MD1210
NR013105
5
Pin Description
V
DD
1
High side analog circuit and level shifter supply voltage. Should be at the same potential as V
DD
2.
V
DD
2
High side gate drive supply voltage
V
SS
1
Low side analog circuit and level shifter supply voltage. Should be at the same potential as V
SS
2.
V
SS
2
Low side gate drive supply voltage
V
H
Supply voltage for P-channel output stage
V
L
Supply voltage for N-channel output stage
GND
Logic input ground reference
OE
Output-enable logic input. When OE is high, (V
OE
+V
GND
)/2 sets the threshold transition between logic level high
and low for INA and INB. When OE is low, OUTA is at V
H
and OUTB is at V
L
regardless of INA and INB.
INA
Logic input. Controls OUTA when OE is high. Input logic high will cause the output to swing to V
L
. Input logic
low will cause the output to swing to V
H
.
INB
Logic input. Controls OUTB when OE is high. Input logic high will cause the output to swing to V
L
. Input logic
low will cause the output to swing to V
H
.
OUTA
Output driver. Swings from V
H
to V
L
. Intended to drive the gate of an external P-channel MOSFET via a series
capacitor. When OE is low, the output is disabled. OUTA will swing to V
H
turning off the external P-channel
MOSFET.
OUTB
Output driver. Swings from V
H
to V
L
. Intended to drive the gate of an external N-channel MOSFET via a series
capacitor. When OE is low, the output is disabled. OUTB will swing to V
L
turning off the external N-channel
MOSFET.
Pin Configuration
Pin #
1
2
3
4
5
6
7
8
9
10
11
12
Function
INA
V
L
INB
GND
V
SS
1
V
SS
2
OUTB
V
H
OUTA
V
DD
2
V
DD
1
OE
Note
Thermal Pad, and substrate are
connected to Pin#5,V
SS
1
Doc.#: DSFP-MD1210 NR013105
QFN-12
4x4x0.9
1
7
12
(Top View, mm)
10
0.30
0.80
2.15
2.15
4
9
6
3
0.55