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參數(shù)資料
| 型號： | MD80C32-30 |
| 廠商： | TEMIC SEMICONDUCTORS |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | 8-BIT, 30 MHz, MICROCONTROLLER, CDIP40 |
| 文件頁數(shù)： | 136/210頁 |
| 文件大?。?/td> | 5175K |
| 代理商： | MD80C32-30 |
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31
8048C–AVR–02/12
ATtiny43U
Idle mode enables the MCU to wake up from external triggered interrupts as well as internal
ones like the Timer Overflow. If wake-up from the Analog Comparator interrupt is not required,
the Analog Comparator can be powered down by setting the ACD bit in the “ACSR – Analog
Comparator Control and Status Register” on page 115. This will reduce power consumption in
Idle mode. If the ADC is enabled, a conversion starts automatically when this mode is entered.
7.1.2
ADC Noise Reduction Mode
When the SM[1:0] bits are written to 01, the SLEEP instruction makes the MCU enter ADC
Noise Reduction mode, stopping the CPU but allowing the ADC, the external interrupts, and the
Watchdog to continue operating (if enabled). This sleep mode halts clk
I/O, clkCPU, and clkFLASH,
while allowing the other clocks to run.
This improves the noise environment for the ADC, enabling higher resolution measurements. If
the ADC is enabled, a conversion starts automatically when this mode is entered. Apart form the
ADC Conversion Complete interrupt, only an External Reset, a Watchdog Reset, a Brown-out
Reset, an SPM/EEPROM ready interrupt, an external level interrupt on INT0 or a pin change
interrupt can wake up the MCU from ADC Noise Reduction mode.
7.1.3
Power-Down Mode
When the SM[1:0] bits are written to 10, the SLEEP instruction makes the MCU enter Power-
down mode. In this mode, the Oscillator is stopped, while the external interrupts, and the Watch-
dog continue operating (if enabled). Only an External Reset, a Watchdog Reset, a Brown-out
Reset, an external level interrupt on INT0, or a pin change interrupt can wake up the MCU. This
sleep mode halts all generated clocks, allowing operation of asynchronous modules only.
7.2
Software BOD Disable
When the Brown-out Detector (BOD) is enabled by BODLEVEL fuses (see Table 19.2 on page
142), the BOD is actively monitoring the power supply voltage during a sleep period. To save
power, it is possible for software to disable the BOD in Power-Down Mode (see “Power-Down
Mode” on page 31). The sleep mode power consumption will then be at the same level as when
BOD is globally disabled by fuses. If disabled by software, the BOD is turned off immediately
after entering the sleep mode and automatically turned on upon wake-up. This ensures safe
operation in case the V
CC level has dropped during the sleep period.
When the BOD has been disabled the wake-up time from sleep mode will be the same as the
wake-up time from RESET. This is in order to ensure the BOD is working correctly before the
MCU continues executing code.
BOD disable is controlled by bit 7 (BODS — BOD Sleep) of MCU Control Register, see “MCUCR
– MCU Control Register” on page 33. Writing this bit to one turns off the BOD in Power-Down
Mode, while a zero in this bit keeps BOD active. The default setting is zero, i.e. BOD active.
Writing to the BODS bit is controlled by a timed sequence and an enable bit, see “MCUCR –
7.3
Power Reduction Register
The Power Reduction Register (PRR), see “PRR – Power Reduction Register” on page 34, pro-
vides a method to stop the clock to individual peripherals to reduce power consumption. The
current state of the peripheral is frozenand the I/O registers can not be read or written.
Resources used by the peripheral when stopping the clock will remain occupied, hence the
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