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參數(shù)資料
| 型號： | MDC5000T1 |
| 廠商： | MOTOROLA INC |
| 元件分類： | 通信及網(wǎng)絡 |
| 英文描述： | SILICON SMALLBLOCK INTEGRATED CIRCUIT |
| 中文描述： | SPECIALTY TELECOM CIRCUIT, PDSO4 |
| 封裝： | SOT-143, 4 PIN |
| 文件頁數(shù)： | 8/10頁 |
| 文件大?。?/td> | 215K |
| 代理商： | MDC5000T1 |
8
Motorola Small–Signal Transistors, FETs and Diodes Device Data
Figure 14. Class A Biasing of a Typical 900 MHz
BJT Amplifier
MDC5000T1
Vref (4)
VCC (3)
Iout (2)
GND (1)
Q1
Q3
MRF9411
Typ
Iout
IC3 = 3 mAdc
Q2
REGULATED VCC = 2.75 Vdc
R5
240
30 nH
18 nH
R1
R2
R3
R4
1 K
9 pF
470 pF
RF IN
8.0 nH
RF OUT
Vref = 2.035 Vdc
470 pF
180
4–STEP DESIGN PROCEDURE
Step 1: Choose VCC (1.8 V Min to 10 V Max)
Step 2: Choose bias current, IC3, and calculate needed Iout from typ HFE3
Step 3: From Figure 1, read Vref for VCC & Iout calculated.
Step 4: Calculate Nominal R5 = (VCC – Vref)
÷
(IC3 + Iout). Tweak as desired.
Figure 15. Class A Biasing of a Typical 890 MHz
Depletion Mode GaAs FET Amplifier
MDC5000T1
Vref (4)
VCC (3)
Iout (2)
GND (1)
Q1
Q3
MRF9811
Typ
Iout
ID = 15 mAdc
Q2
REGULATED VCC = 2.75 Vdc
6.8 nH
2.7 pF
R1
R2
R3
R4
1 K
6.1 pF
1000 pF
RF IN
12.5 nH
RF OUT
Vref = 2.100 Vdc
1000 pF
6–STEP DESIGN PROCEDURE
Step 1: Choose VCC (1.8 V Min to 10 V Max)
Step 2: Choose bias current, ID, and determine needed gate–source voltage, VGS.
Step 3: Choose Iout keeping in mind that too large an Iout can impair MDC5000T1 Vref/ TJ
performance (Figure 2) but too large an R6 can cause IDGO & IGSO to bias on the FET.
Step 4: Calculate R6 = (VGS + EGS)
÷
Iout
Step 5: From Figure 1, read Vref for VCC & Iout chosen
Step 6: Calculate Nominal R5 = (VCC – Vref)
÷
(ID + Iout). Tweak as desired.
RFC
R5
43
+
R6
22 K
EGS
5 Vdc
D
S
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