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參數(shù)資料
| 型號(hào)： | MDC5001T1 |
| 廠商： | MOTOROLA INC |
| 元件分類： | 通信及網(wǎng)絡(luò) |
| 英文描述： | SILICON SMALLBLOCK INTEGRATED CIRCUIT |
| 中文描述： | SPECIALTY TELECOM CIRCUIT, PDSO6 |
| 封裝： | SOT-363, 6 PIN |
| 文件頁(yè)數(shù)： | 8/10頁(yè) |
| 文件大小： | 188K |
| 代理商： | MDC5001T1 |
8
Motorola Small–Signal Transistors, FETs and Diodes Device Data
APPLICATION CIRCUITS
Figure 18. Class A Biasing of a Typical 900 MHz
BJT Amplifier Application
Q3
MRF9411
Typ
Iout
IC3 = 3 mAdc
REGULATED VCC = 2.75 Vdc
R5
240
30 nH
18 nH
1 K
9 pF
470 pF
RF IN
8.0 nH
RF OUT
Vref = 2.025 Vdc
470 pF
180
5–STEP DESIGN PROCEDURE
Step 1: Choose VCC (1.8 V Min to 10 V Max)
Step 2: Insure that Min VENBL is
≥
minimum indicated in Figures 5 and 6.
Step 3: Choose bias current, IC3, and calculate needed Iout from typ HFE3
Step 4: From Figure 1, read Vref for VCC and Iout calculated.
Step 5: Calculate Nominal R5 = (VCC – Vref)
(IC3 + Iout). Tweak as desired.
MDC5001
VCC (4)
GND (2) & (3)
Q1
Q2
+
VCC = 2.75 V
Q4
Vref (6)
Iout (1)
ENABLE
(5)
VENBL
Figure 19. Class A Biasing of a Typical 890 MHz
Depletion Mode GaAs FET Amplifier
Q3
MRF9811
Typ
Iout
ID = 15 mAdc
REGULATED VCC = 2.75 Vdc
6.8 nH
2.7 pF
1 K
6.1 pF
1000 pF
RF IN
12.5 nH
RF OUT
Vref = 2.085 Vdc
1000 pF
7–STEP DESIGN PROCEDURE
Step 1: Choose VCC (1.8 V Min to 10 V Max)
Step 2: Insure that Min VENBL is
≥
minimum indicated in Figures 5 and 6.
Step 3: Choose bias current, ID, and determine needed gate–source voltage, VGS.
Step 4: Choose Iout keeping in mind that too large an Iout can impair MDC5000 Vref/ TJ
performance (Figure 2) but too large an R6 can cause IDGO & IGSO to bias on the FET.
Step 5: Calculate R6 = (VGS + EGS)
Iout
Step 6: From Figure 1, read Vref for VCC & Iout chosen
Step 7: Calculate Nominal R5 = (VCC – Vref)
(ID + Iout). Tweak as desired.
RFC
R5
43
+
R6
22 K
EGS
5 Vdc
MDC5001
VCC (4)
GND (2) & (3)
Q1
Q2
+
VCC =
2.75 V
Q4
Vref (6)
Iout (1)
ENABLE
(5)
VENBL
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