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參數(shù)資料
| 型號(hào)： | MF1S5035DUD |
| 廠商： | NXP Semiconductors N.V. |
| 元件分類： | 外設(shè)及接口 |
| 英文描述： | MIFARE Classic 1K - Mainstream contactless smart card IC for fast and easy solution development |
| 封裝： | MF1S5030DA3<SOT500|<<<1<Always Pb-free,;MF1S5030DA4<SOT500-2 (PLLMC)|<<http://www.nxp.com/packages/SOT500-2.html<1<Always Pb-free,;MF1S5030DA6<SOT500-3 (PLLMC)|& |
| 文件頁(yè)數(shù)： | 24/37頁(yè) |
| 文件大?。?/td> | 425K |
| 代理商： | MF1S5035DUD |
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MF1S503x
All information provided in this document is subject to legal disclaimers.
NXP B.V. 2011. All rights reserved.
Product data sheet
PUBLIC
Rev. 3.1 — 21 February 2011
194031
24 of 37
NXP Semiconductors
MF1S503x
MIFARE Classic 1K - Mainstream contactless smart card IC
[1]
the gap between chips may vary due to changing foil expansion
Table 26.
Bond pads (substrate connected to VSS)
size (metallization)
[1]
Pads VSS and TESTIO are disconnected when wafer is sawn.
Table 27.
Au bump (substrate connected to VSS)
material
[1]
Pads VSS and TESTIO are disconnected when wafer is sawn.
13.1 Fail die identification
Electronic wafer mapping covers the electrical test results and additionally the results of
mechanical/visual inspection.
No ink dots are applied.
Passivation
type
material
thickness
sandwich structure
PSG / nitride
500 nm / 600 nm
Bond pad specifications
LA, LB, VSS
[1]
= 118
μ
m
×
118
μ
m
TESTIO
[1]
= 103
μ
m
×
118
μ
m
LA, LB, VSS
[1]
= 90
μ
m
×
90
μ
m
TESTIO
[1]
= 75
μ
m
×
90
μ
m
Al-Cu
850 nm
size (pad opening)
material
thickness
Bump specifications
>
99.9 % pure Au
35 to 80 HV 0.005
> 70 MPa
18
μ
m
within a die =
±
2
μ
m
within a wafer =
±
3
μ
m
wafer to wafer =
±
4
μ
m
minimum =
±
1.5
μ
m
LA, LB, VSS
[1]
= 104
μ
m
×
104
μ
m
TESTIO
[1]
= 89
μ
m
×
104
μ
m
±
5
μ
m
sputtered TiW
hardness
shear strength
height
height uniformity
flatness
size
size variation
under bump metallization
Table 25.
Wafer specifications MF1S5037DUx
…continued
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