參數(shù)資料
型號(hào)： MG65P
廠商： OKI SEMICONDUCTOR CO., LTD.
英文描述： 0.25レm Embedded DRAM/ Customer Structured Arrays
中文描述： 0.25レ米嵌入式DRAM /客戶(hù)結(jié)構(gòu)數(shù)組
文件頁(yè)數(shù)： 5/22頁(yè)
文件大?。?/td> 267K
代理商： MG65P
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I
MG63P/64P/65P
I
3
Oki Semiconductor
MG63P/64P/65P CSA Layout Methodology
The procedure to design, place, and route a CSA follows.
1. Select suitable base array frame from the available predefined sizes. To select an array size:
- Identify megacell functions (e.g. embedded SDRAM) required and minimum array size to
hold macrocell functions.
- Add together all the area occupied by the required random logic and macrocells and select
the optimum array.
2. Make a floor plan for the design’s megacells.
- Oki Design Center engineers verify the master slice and review simulation.
- Oki Design Center or customer engineers floorplan the array using Oki’s supported Cadence
DP3 or Gambit GFP and customer performance specifications.
- Using Oki CAD software, Design Center engineers remove the SOG transistors and replace
them with diffused memory macrocells to the customer’s specifications.
Core base cell
with 4 transistors
Separate power bus (V
, V
) over I/O cell
for output buffers (2nd metal/3rd metal)
V
, V
pads (4) in each
corner for wafer probing only
Configurable I/O pads
for V
DD
, V
SS
, or I/O
Separate power bus (V
, V
) for
internal core logic (2nd metal/3rd metal)
I/O base cells
1, 2, 3, 4, or 5 layer
metal
interconnection in
core area
Figure 7. MG65P Array Architecture
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