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參數(shù)資料
| 型號(hào)： | MG65P |
| 廠商： | OKI SEMICONDUCTOR CO., LTD. |
| 英文描述： | 0.25レm Embedded DRAM/ Customer Structured Arrays |
| 中文描述： | 0.25レ米嵌入式DRAM /客戶結(jié)構(gòu)數(shù)組 |
| 文件頁(yè)數(shù)： | 6/22頁(yè) |
| 文件大小： | 267K |
| 代理商： | MG65P |
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MG63P/64P/65P
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4
Oki Semiconductor
Figure 8
shows an array base after placement of the optimized memory macrocells.
3. Place and route logic into the array transistors.
- Oki Design Center engineers use layout software and customer performance specifications
to connect the random logic and optimized memory macrocells.
Figure 9
marks the area in which placement and routing is performed with cross hatching.
Figure 10
illustrates Oki’s Embedded DRAM ASIC. Oki provides two types of reconfigurable SDRAM
cores generated from the compiler.
Figure 8. Optimized Memory Macrocell Floor Plan
Mega macrocells
High-density SRAM
Embedded SDRAM
Figure 9. Random Logic Place and Route
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