參數(shù)資料
型號： MH16D72AKLB-75
廠商： Mitsubishi Electric Corporation
英文描述： JT 41C 41#20 PIN GRND PLUG
中文描述： 1,207.959,552位（16,777,216 - Word的72位），雙數(shù)據(jù)速率同步DRAM模塊
文件頁數(shù)： 16/39頁
文件大?。?/td> 348K
代理商： MH16D72AKLB-75
MITSUBISHI LSIs
MITSUBISHI ELECTRIC
MH16D72AKLB-10,75
1,207.959,552-BIT (16,777,216-WORD BY 72-BIT) Double Data Rate Synchronous DRAM Module
MIT-DS-0397-1.1
24.Nov.2000
Preliminary Spec.
Some contents are subject to change without notice.
16
ABSOLUTE MAXIMUM RATINGS
DC OPERATING CONDITIONS
(Ta=0 ~ 70 , unless otherwise noted)
C
CAPACITANCE
(Ta=0 ~ 70 , Vdd = VddQ = 2.5 ± 0.2V, Vss = VssQ = 0V, unless otherwise noted)
Symbol
Parameter
Conditions
Ratings
Unit
Vdd
Supply Voltage
with respect to Vss
-0.5 ~ 3.7
V
VddQ
Supply Voltage for Output
with respect to VssQ
-0.5 ~ 3.7
V
VI
Input Voltage
with respect to Vss
-0.5 ~ Vdd+0.5
V
VO
Output Voltage
with respect to VssQ
-0.5 ~ VddQ+0.5
V
IO
Output Current
50
mA
Pd
Power Dissipation
Ta = 25
W
Topr
Operating Temperature
0 ~ 70
Tstg
Storage Temperature
-45 ~ 100
Symbol
Parameter
Limits
Unit
Min.
Typ.
Max.
Vdd
Supply Voltage
2.3
2.5
2.7
V
VddQ
Supply Voltage for Output
2.3
2.5
2.7
V
VIH(DC)
High-Level Input Voltage
Vref + 0.18
VddQ+0.3
V
VIL(DC)
Low-Level Input Voltage
-0.3
Vref - 0.18
V
Vref
Input Reference Voltage
1.15
1.35
V
1.25
VIN(DC)
Input Voltage Level, CK0 and /CK0
-0.3
VddQ + 0.3
V
VID(DC) Input Differential Voltage, CK0 and /CK0
0.36
VddQ + 0.6
V
VTT
I/O Termination Voltage
Vref - 0.04
V
Vref + 0.04
Notes
6
5
7
C
C
C
Symbol
CI(A)
CI(C)
CI(K)
CI/O
Parameter
Input Capacitance, address pin
Input Capacitance, control pin
Input Capacitance, CK0 pin
Input Capacitance, I/O pin
Test Condition
Limits(max.)
8.0
Unit
pF
pF
VI - 1.25V
f=100MHz
VI = 25mVrm
pF
pF
8.0
15.3
13.3
O
O
10
Notes
11
11
11
11
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