參數(shù)資料
型號: MH32D64KQH-75
廠商: Mitsubishi Electric Corporation
英文描述: 5.0 A 1.0MHZ FULLY INTEG
中文描述: 2147483648位(33554432字64位),雙數(shù)據(jù)速率同步DRAM模塊
文件頁數(shù): 32/40頁
文件大?。?/td> 350K
代理商: MH32D64KQH-75
MH32D64KQH-75,-10
2,147,483,648-BIT (33,554,432-WORD BY 64-BIT) Double Data Rate Synchronous DRAM Module
MIT-DS-0417-0.2
17.May.2001
Preliminary Spec.
Some contents are subject to change without notice.
MITSUBISHI LSIs
MITSUBISHI
ELECTRIC
32
[Initialize and Mode Register sets]
Command
/CLK
CLK
EMRS
PRE
NOP
MRS
PRE
AR
AR
MRS
ACT
Code
Code
Xa
Code
Xa
1 0
Xa
A0-9,11-12
A10
Code
1
BA0,1
DQS
DQ
1
0 0
0 0
Code
tMRD
tMRD
tRP
tRFC
tRFC
tMRD
[AUTO REFRESH]
Single cycle of auto-refresh is initiated with a REFA(/CS=/RAS=/CAS=L,/WE=CKE=H) command. The
refresh address is generated internally. 8192 REFA cycles within 64ms refresh 256Mbits memory cells.
The auto-refresh is performed on 4 banks concurrently. Before performing an auto refresh, all banks must
be in the idle state. Auto-refresh to auto-refresh interval is minimum tRFC . Any command must not be
supplied to the device before tRFC from the REFA command.
Auto-Refresh
/RAS
CKE
/CS
/CAS
/WE
A0-12
BA0,1
NOP or DESELECT
tRFC
Auto Refresh on All Banks
Auto Refresh on All Banks
/CLK
CLK
Extended Mode
Register Set
Mode Register Set,
Reset DLL
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