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參數(shù)資料
| 型號： | MH32V7245BST-5 |
| 廠商： | Mitsubishi Electric Corporation |
| 英文描述： | HYPER PAGE MODE 2415919104 - BIT ( 33554432 - WORD BY 72 - BIT ) DYNAMIC RAM |
| 中文描述： | 超頁模式2415919104 -位（33554432 - Word的72 -位）動態(tài)隨機存儲器 |
| 文件頁數(shù)： | 1/22頁 |
| 文件大?。?/td> | 138K |
| 代理商： | MH32V7245BST-5 |
MITSUBISHI LSIs
MH32V7245BST -5, -6
Preliminary Spec.
MITSUBISHI
ELECTRIC
13/JUL./1998
HYPER PAGE MODE 2415919104 - BIT ( 33554432 - WORD BY 72 - BIT ) DYNAMIC RAM
MIT - DS - 0218-0.0
DESCRIPTION
The MH32V7245BST is 33554432-word x 72-bit dynamic
ram stacked structural module. This consist of thirty-six
industry standard 16M x 4 dynamic RAMs in TSOP and
two industry standard input buffer in TSSOP.
The stacked structure of TSOP on a card edge dual in-line
package provides any application where high densities and
large of quantities memory are required.
This is a socket-type memory module ,suitable for easy
interchange or addition of module.
FEATURES
MH32V7245BST-5
MH32V7245BST-6
Type name
/RAS
access
time
(max.ns)
/CAS
access
time
(max.ns)
Address
access
time
(max.ns)
/OE
access
time
(max.ns)
Cycle
Power
time
(min.ns)
dissipation
(typ.W)
50
60
18
20
30
35
18
20
84
110
Utilizes industry standard 16M x 4 RAMs TSOP and industry
standard input buffer in TSSOP
168-pin (84-pin dual dual in-line package) stacked structure
Single 3.3V(+/- 0.3V) supply operation
Low stand-by power dissipation . . . . . . . . . . 64.9mW(Max)
Low operation power dissipation
MH32V7245BST -5 . . . . . . . . . . . . . . . . . . 8.44W(Max)
MH32V7245BST -6 . . . . . . . . . . . . . . . . . . 7.79W(Max)
All input are directly LVTTL compatible
All output are three-state and directry LVTTL compatible
Includes(0.22 uF x 38) decoupling capacitors
4096 refresh cycle every 64ms (A0 - A11)
Hyper-page mpde,Read-modify-write,/CAS before /RAS refresh,
Hidden refresh capabilities
JEDEC standard pin configration & Buffered PD pin
Buffered input except /RAS and DQ
Gold plating contact pads
APPLICATION
Main memory unit for computers , Microcomputer memory
PD&ID TABLE
PD1 PD2 PD3 PD4 PD5 PD6 PD7 PD8 ID0
1
0
0
0
1
1
0
0
0
1
1
0
0
0
1
ID1
0
0
0
- 6
- 7
- 5
1 = NC , 0 = drive to VOL
PD pin . . . buffered. When /PDE is low, PD information can be read
ID pin . . . non-buffered
0
1
0
0
1
1
0
0
0
0
0
0
7.03
5.87
PIN CONFIGURATION
1pin
10pin
11pin
40pin
41pin
84pin
85pin
94pin
95pin
124pin
125pin
168pin
FRONT SIDE
BACK SIDE
1
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