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參數(shù)資料
| 型號： | MH4S64CBMD-10B |
| 廠商： | Mitsubishi Electric Corporation |
| 英文描述： | 268435456-BIT (4194304-WORD BY 64-BIT)SynchronousDRAM |
| 中文描述： | 268435456位（4194304字，64位）SynchronousDRAM |
| 文件頁數(shù)： | 26/55頁 |
| 文件大小： | 586K |
| 代理商： | MH4S64CBMD-10B |
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MH4S64BLG -7,-8,-10
268435456-BIT (4194304 - WORD BY 64-BIT)SynchronousDRAM
MITSUBISHI LSIs
( 26
MITSUBISHI
ELECTRIC
29.Oct.1998
Preliminary Spec.
Some contents are subject to change without notice.
MIT-DS-0227-0.5
SELF REFRESH
Self-refresh mode is entered by issuing a REFS command (/CS=/RAS=/CAS=L,
/WE=H, CKE=L). Once the self-refresh is initiated, it is maintained as log as CKE is
kept low.During the self-refresh mode, CKE is asynchronous and the only enabled
input , all other inputs including CK are disabled and ignored, so that power
consumption due to synchronous inputs is saved. To exit the self-refresh, supplying
stable CK inputs, asserting DESEL or NOP command and then asserting
CKE(REFSX) for longer than tSRX. After tRC from REFSX all banks are in the idle
state and a new command can be issued after tRC, but DESEL or NOP commands
must be asserted till then.
Self-Refresh
CK
/S
/RAS
/CAS
/WE
CKE
A0-11
BA0,1
Self Refresh Entry
Self Refresh Exit
X
00
minimum tRC
+1 CLOCK
for recovery
Stable CK
NOP
new command
tSRX
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