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參數(shù)資料
| 型號(hào)： | MH64D64AKQH-10 |
| 廠商： | Mitsubishi Electric Corporation |
| 元件分類： | 圓形連接器 |
| 英文描述： | Circular Connector; No. of Contacts:55; Series:MS27484; Body Material:Aluminum; Connecting Termination:Crimp; Connector Shell Size:22; Circular Contact Gender:Socket; Circular Shell Style:Straight Plug; Insert Arrangement:22-55 RoHS Compliant: No |
| 中文描述： | 4294967296位（67108864字64位），雙數(shù)據(jù)速率同步DRAM模塊 |
| 文件頁數(shù)： | 25/40頁 |
| 文件大?。?/td> | 362K |
| 代理商： | MH64D64AKQH-10 |
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MH64D64AKQH-75,-10
4,294,967,296-BIT (67,108,864-WORD BY 64-BIT) Double Data Rate Synchronous DRAM Module
MIT-DS-0418-0.1
17.May.2001
Preliminary Spec.
Some contents are subject to change without notice.
MITSUBISHI LSIs
MITSUBISHI
ELECTRIC
25
WRITE
After tRCD from the bank activation, a WRITE command can be issued. 1st input data is set from the
WRITE command with data strobe input, following (BL-1) data are written into RAM, when the Burst
Length is BL. The start address is specified by A9-A0, and the address sequence of burst data is defined
by the Burst Type. A WRITE command may be applied to any active bank, so the row precharge time
(tRP) can be hidden behind continuous input data by interleaving the multiple banks. From the last data to
the PRE command, the write recovery time (tWRP) is required. When A10 is high at a WRITE command,
the auto-precharge(WRITEA) is performed. Any command(READ,WRITE,PRE,ACT) to the same bank
is inhibited till the internal precharge is complete. The next ACT command can be issued after tDAL from
the last input data cycle.
WRITE with Auto-Precharge (BL=8)
Command
A0-9,11-12
A10
BA0,1
DQ
ACT
Xa
00
WRITE
1
00
ACT
Xb
00
tRCD
Da0
DQS
/CLK
CLK
Da1
Da2
Da3
Da4
Da5
Da6
Da7
tDAL
Xa
Y
Xb
Multi Bank Interleaving WRITE (BL=8)
Command
A0-9,11-12
A10
BA0,1
DQ
ACT
Xa
00
WRITE
00
WRITE
0
0
10
ACT
Xb
10
0
10
tRCD
tRCD
PRE
0
00
PRE
DQS
/CLK
CLK
Da0
Da1
Da2
Da3
Da4
Da5
Da6
Da7
Db0
Db1
Db2
Db3
Db4
Db5
Db6
Db7
Xa
Ya
Yb
Xb
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| MH64D64AKQH-75 | Circular Connector; No. of Contacts:128; Series:MS27484; Body Material:Aluminum; Connecting Termination:Crimp; Connector Shell Size:24; Circular Contact Gender:Pin; Circular Shell Style:Straight Plug; Insert Arrangement:24-35 RoHS Compliant: No |
| MH88422BD-1 | Data Access Arrangement Preliminary Information |
| MH88422 | Line Interface Circuit Preliminary Information |
| MH88422-1 | Data Access Arrangement Preliminary Information |
| MH88422-2 | Data Access Arrangement Preliminary Information |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| MH64D64AKQH-75 | 制造商:MITSUBISHI 制造商全稱:Mitsubishi Electric Semiconductor 功能描述:4,294,967,296-BIT (67,108,864-WORD BY 64-BIT) Double Data Rate Synchronous DRAM Module |
| MH64D72KLG-10 | 制造商:MITSUBISHI 制造商全稱:Mitsubishi Electric Semiconductor 功能描述:4,831,838,208-BIT (67,108,864-WORD BY 72-BIT) Double Data Rate Synchronous DRAM Module |
| MH64D72KLG-75 | 制造商:MITSUBISHI 制造商全稱:Mitsubishi Electric Semiconductor 功能描述:4,831,838,208-BIT (67,108,864-WORD BY 72-BIT) Double Data Rate Synchronous DRAM Module |
| MH64D72KLH-10 | 制造商:MITSUBISHI 制造商全稱:Mitsubishi Electric Semiconductor 功能描述:4,831,838,208-BIT (67,108,864-WORD BY 72-BIT) Double Data Rate Synchronous DRAM Module |
| MH64D72KLH-75 | 制造商:MITSUBISHI 制造商全稱:Mitsubishi Electric Semiconductor 功能描述:4,831,838,208-BIT (67,108,864-WORD BY 72-BIT) Double Data Rate Synchronous DRAM Module |
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