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參數(shù)資料
| 型號： | MH64S64APFH-7L |
| 廠商： | Mitsubishi Electric Corporation |
| 英文描述： | 4294967296-BIT (67108864 - WORD BY 64-BIT)SynchronousDRAM |
| 中文描述： | 4294967296位（67108864 -文字，64位）SynchronousDRAM |
| 文件頁數(shù)： | 19/52頁 |
| 文件大?。?/td> | 604K |
| 代理商： | MH64S64APFH-7L |
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MITSUBISHI LSIs
( 19
MITSUBISHI
ELECTRIC
Preliminary Spec.
Some contents are subject to change without notice.
MIT-DS-0392-0.1
MH64S64APFH-6,-6L,-7,-7L
4294967296-BIT (67108864 - WORD BY 64-BIT)SynchronousDRAM
16.Apr.2000
WRITE (BL=4)
CK
Command
A10
DQ
ACT
Xa
Xa
00
Write
Ya
0
00
Da0
Da1
Da2
Da3
PRE
0
tRCD
BL
CK
Command
A10
DQ
ACT
Xa
Xa
00
Write
Ya
1
00
Da0
Da1
Da2
Da3
ACT
Xa
Xa
00
Internal precharge begins
tRCD
tRP
WRITE with Auto-Precharge (BL=4)
WRITE
A WRITE command can be issued to any active bank. The start address is specified by A0-9
(x8). 1st input data is set at the same cycle as the WRITE. The consecutive data length to be
written is defined by the Burst Length. The address sequence of burst data is defined by the
Burst Type. Minimum delay time of a WRITE command after an ACT command to the same
bank is tRCD. From the last input data to the PRE command, the write recovery time (tWR) is
required. When A10 is high at a WRITE command, auto-precharge (WRITEA) is performed.
Any command (READ, WRITE, PRE, ACT, TBST) to the same bank is inhibited till the internal
precharge is complete. The internal precharge starts at tWR after the last input data cycle.
The next ACT command can be issued after (BL + tWR -1 + tRP) from the previous WRITEA.
In any case, tRCD + BL + tWR -1 > tRASmin must be met.
A0-9, 11-12
BA0,1
A0-9, 11-12
BA0,1
ACT
Xa
00
tWR
tRP
Xa
tWR
BL
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| MH64S72AWJA-6 | 制造商:MITSUBISHI 制造商全稱:Mitsubishi Electric Semiconductor 功能描述:4,831,838,208-BIT ( 67,108,864-WORD BY 72-BIT ) Synchronous DYNAMIC RAM |
| MH64S72AWJA-7 | 制造商:MITSUBISHI 制造商全稱:Mitsubishi Electric Semiconductor 功能描述:4,831,838,208-BIT ( 67,108,864-WORD BY 72-BIT ) Synchronous DYNAMIC RAM |
| MH64S72AWJA-8 | 制造商:MITSUBISHI 制造商全稱:Mitsubishi Electric Semiconductor 功能描述:4,831,838,208-BIT ( 67,108,864-WORD BY 72-BIT ) Synchronous DYNAMIC RAM |
| MH64S72QJA-6 | 制造商:MITSUBISHI 制造商全稱:Mitsubishi Electric Semiconductor 功能描述:4,831,838,208-BIT ( 64,108,864-WORD BY 72-BIT ) Synchronous DYNAMIC RAM |
| MH64S72QJA-7 | 制造商:MITSUBISHI 制造商全稱:Mitsubishi Electric Semiconductor 功能描述:4,831,838,208-BIT ( 67,108,864-WORD BY 72-BIT ) Synchronous DYNAMIC RAM |
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