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參數(shù)資料
| 型號(hào)： | MH64S72QJA-6 |
| 廠商： | Mitsubishi Electric Corporation |
| 英文描述： | 4,831,838,208-BIT ( 64,108,864-WORD BY 72-BIT ) Synchronous DYNAMIC RAM |
| 中文描述： | 4831838208位（64108864 - Word的72位）同步動(dòng)態(tài)隨機(jī)存儲(chǔ)器 |
| 文件頁數(shù)： | 53/56頁 |
| 文件大?。?/td> | 936K |
| 代理商： | MH64S72QJA-6 |
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4,831,838,208-BIT ( 67,108,864-WORD BY 72-BIT ) Synchronous DYNAMIC RAM
MH64S72AWJA -6,-7,-8
17/Mar. /2000
MIT-DS-372-0.2
Preliminary Spec.
Some contents are subject to change without notice.
MITSUBISHI LSIs
MITSUBISHI
ELECTRIC
53
Serial Presence Detect Table I
Byte
0
1
2
3
4
5
6
7
8
9
Function described
SPD enrty data
128
256 Bytes
SDRAM
A0-A11
SPD DATA(hex)
Defines # bytes written into serial memory at module mfgr
Total # bytes of SPD memory device
Fundamental memory type
# Row Addresses on this assembly
# Column Addresses on this assembly
# Module Banks on this assembly
Data Width of this assembly...
... Data Width continuation
Voltage interface standard of this assembly
SDRAM Cycletime at Max. Supported CAS Latency (CL).
Cycle time for CL=3
80
08
04
0C
A0-A10
2BANK
0B
02
x72
0
LVTTL
7.5ns
48
00
01
75
A0
54
10
SDRAM Access from Clock
tAC for CL=3
DIMM Configuration type (Non-parity,Parity,ECC)
Refresh Rate/Type
6ns
60
11
12
13
14
15
16
17
ECC
02
80
self refresh(15.625uS)
SDRAM width,Primary DRAM
Error Checking SDRAM data width
x4
x4
04
04
01
8F
04
Minimum Clock Delay,Back to Back Random Column Addresses
1
Burst Lengths Supported
1/2/4/8/Full page
# Banks on Each SDRAM device
4bank
18
CAS# Latency
19
20
21
22
CS# Latency
Write Latency
0
0
01
01
1F
0E
A0
SDRAM Module Attributes
SDRAM Device Attributes:General
Precharge All,Auto precharge
10ns
23
SDRAM Cycle time(2nd highest CAS latency)
Cycle time for CL=2
13ns
6ns
D0
60
24
SDRAM Access form Clock(2nd highest CAS latency)
7ns
70
tAC for CL=2
25
26
SDRAM Cycle time(3rd highest CAS latency)
N/A
00
N/A
22.5ns
00
17
SDRAM Access form Clock(3rd highest CAS latency)
27
Precharge to Active Minimum
20ns
14
28
Row Active to Row Active Min.
15ns
20ns
0F
14
10ns
5.4ns
-8
-8
-7
10ns
A0
6ns
60
-7
29
RAS to CAS Delay Min
22.5ns
20ns
45ns
17
14
2D
30
Active to Precharge Min
50ns
32
-7,-8
-6
-7,-8
-6
2/3
06
-6
-6
-7,-8
-6
-7,-8
-6
-7,-8
-6
-7,-8
-6
buffered,registered
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相關(guān)代理商/技術(shù)參數(shù) |
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|---|---|
| MH64S72QJA-7 | 制造商:MITSUBISHI 制造商全稱:Mitsubishi Electric Semiconductor 功能描述:4,831,838,208-BIT ( 67,108,864-WORD BY 72-BIT ) Synchronous DYNAMIC RAM |
| MH64S72QJA-8 | 制造商:MITSUBISHI 制造商全稱:Mitsubishi Electric Semiconductor 功能描述:4,831,838,208-BIT ( 67,108,864-WORD BY 72-BIT ) Synchronous DYNAMIC RAM |
| MH64S72VJG-5 | 制造商:MITSUBISHI 制造商全稱:Mitsubishi Electric Semiconductor 功能描述:4,831,838,208-BIT ( 67,108,864-WORD BY 72-BIT ) Synchronous DYNAMIC RAM |
| MH64S72VJG-6 | 制造商:MITSUBISHI 制造商全稱:Mitsubishi Electric Semiconductor 功能描述:4,831,838,208-BIT ( 67,108,864-WORD BY 72-BIT ) Synchronous DYNAMIC RAM |
| MH64TAD | 制造商:MTRONPTI 制造商全稱:MTRONPTI 功能描述:8 pin DIP, 3.3 or 5.0 Volt, HCMOS/TTL Clock Oscillator |
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