參數(shù)資料
型號: MH64S72QJA-8
廠商: Mitsubishi Electric Corporation
英文描述: 4,831,838,208-BIT ( 67,108,864-WORD BY 72-BIT ) Synchronous DYNAMIC RAM
中文描述: 4831838208位(67108864 - Word的72位)同步動態(tài)隨機存儲器
文件頁數(shù): 16/56頁
文件大?。?/td> 936K
代理商: MH64S72QJA-8
4,831,838,208-BIT ( 67,108,864-WORD BY 72-BIT ) Synchronous DYNAMIC RAM
MH64S72AWJA -6,-7,-8
17/Mar. /2000
MIT-DS-372-0.2
Preliminary Spec.
Some contents are subject to change without notice.
MITSUBISHI LSIs
MITSUBISHI
ELECTRIC
AC TIMING REQUIREMENTS
(Ta=0 ~ 70°C, Vdd = 3.3 +/- 0.3V, Vss = 0V, unless otherwise noted)
Input Pulse Levels: 0.8V to 2.0V
Input Timing Measurement Level: 1.4V
LATCH MODE
CK
Signal
1.4V
1.4V
Any AC timing is
referenced to the input
signal crossing
through 1.4V.
16
Limits
-7
Min.
Symbol Parameter
Unit
Max.
tCLK
CK cycle time
ns
ns
tCH
tCL
tT
tIS
tIH
tRC
tRCD
tRAS
tRP
tWR
tRRD
tRSC
tSRX
tPDE
CK High pulse width
CK Low pilse width
Transition time of CK
Input Setup time(all inputs)
Input Hold time(all inputs)
Row cycle time
Row to Column Delay
Row Active time
Row Precharge time
Write Recovery time
Act to Act Deley time
Mode Register Set Cycle time
Self Refresh Exit time
Power Down Exit time
3
3
1
2
1
10
10
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
10
70
20
50
20
20
20
20
10
10
100K
tREF
Refresh Interval time
64
ms
-8
Min.
Max.
3
3
1
2
1
13
10
10
70
20
50
20
20
20
20
10
10
100K
64
CL=3
CL=4
-6
Min.
Max.
2.5
2.5
10
7.5
1
10
1.5
0.8
67.5
20
45
20
15
15
15
7.5
7.5
100K
64
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