參數(shù)資料
型號(hào): MK10N512VML100
廠商: FREESCALE SEMICONDUCTOR INC
元件分類: 微控制器/微處理器
英文描述: RISC MICROCONTROLLER, PBGA104
封裝: 8 X 8 MM, MAPBGA-104
文件頁(yè)數(shù): 50/60頁(yè)
文件大小: 877K
代理商: MK10N512VML100
8 Pinout
8.1 K10 Signal Multiplexing and Pin Assignments
The following table shows the signals available on each pin and the locations of these
pins on the devices supported by this document. The Port Control Module is responsible
for selecting which ALT functionality is available on each pin.
100
QFP
Default
ALT0
ALT1
ALT2
ALT3
ALT4
ALT5
ALT6
ALT7
EzPort
1
ADC1_SE4a
PTE0
SPI1_PCS1
UART1_TX
SDHC0_D1
I2C1_SDA
2
ADC1_SE5a
PTE1
SPI1_SOUT
UART1_RX
SDHC0_D0
I2C1_SCL
3
ADC1_SE6a
PTE2
SPI1_SCK
UART1_CTS_
b
SDHC0_DCLK
4
ADC1_SE7a
PTE3
SPI1_SIN
UART1_RTS_
b
SDHC0_CMD
5
DISABLED
PTE4
SPI1_PCS0
UART3_TX
SDHC0_D3
6
DISABLED
PTE5
SPI1_PCS2
UART3_RX
SDHC0_D2
7
DISABLED
PTE6
SPI1_PCS3
UART3_CTS_
b
I2S0_MCLK
I2S0_CLKIN
8
VDD
9
VSS
10
ADC0_SE4a
PTE16
SPI0_PCS0
UART2_TX
FTM_CLKIN0
FTM0_FLT3
11
ADC0_SE5a
PTE17
SPI0_SCK
UART2_RX
FTM_CLKIN1
LPT00_ALT3
12
ADC0_SE6a
PTE18
SPI0_SOUT
UART2_CTS_
b
I2C0_SDA
13
ADC0_SE7a
PTE19
SPI0_SIN
UART2_RTS_
b
I2C0_SCL
14
ADC0_DP1
15
ADC0_DM1
16
ADC1_DP1
17
ADC1_DM1
18
PGA0_DP/
ADC0_DP0/
ADC1_DP3
PGA0_DP/
ADC0_DP0/
ADC1_DP3
19
PGA0_DM/
ADC0_DM0/
ADC1_DM3
PGA0_DM/
ADC0_DM0/
ADC1_DM3
20
PGA1_DP/
ADC1_DP0/
ADC0_DP3
PGA1_DP/
ADC1_DP0/
ADC0_DP3
21
PGA1_DM/
ADC1_DM0/
ADC0_DM3
PGA1_DM/
ADC1_DM0/
ADC0_DM3
Pinout
K10 Sub-Family Data Sheet Data Sheet, Rev. 1, 11/2010.
54
Preliminary
Freescale Semiconductor, Inc.
Preliminary
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