參數(shù)資料
型號: MK1574-01SLF
廠商: IDT, Integrated Device Technology Inc
文件頁數(shù): 6/10頁
文件大小: 0K
描述: IC PLL FRAME RATE COMM 16-SOIC
標準包裝: 48
類型: 時鐘/頻率合成器
PLL:
輸入: 時鐘
輸出: CMOS
電路數(shù): 1
比率 - 輸入:輸出: 1:3
差分 - 輸入:輸出: 無/無
頻率 - 最大: 8kHz
除法器/乘法器: 無/是
電源電壓: 3 V ~ 3.6 V
工作溫度: 0°C ~ 70°C
安裝類型: 表面貼裝
封裝/外殼: 16-SOIC(0.154",3.90mm 寬)
供應商設(shè)備封裝: 16-SOIC
包裝: 管件
MK1574
3.3 VOLT FRAME RATE COMMUNICATIONS PLL
CLOCK SYNTHESIZER
IDT / ICS 3.3 VOLT FRAME RATE COMMUNICATIONS PLL
5
MK1574
REV F 111605
AC Electrical Characteristics
VDD = 3.3 V, Ambient Temperature 0 to +70
°C, unless stated otherwise
Note 1: All multipliers as shown in the table on page two are exact, and are stored in ROM on the chip.
Thermal Characteristics
Loop Bandwidth and Loop Filter Component Selection
The series-connected capacitor and resistor between CAP1 and CAP2 (pins 4 and 6) determine the dynamic
characteristics of the phase-locked loop. The capacitor must have very low leakage, therefore a high quality
ceramic capacitor is recommended. DO NOT use any type of polarized or electrolytic capacitor. The series
connected capacitor and resistor between CAP1 and CAP2 (pins 4 and 6) determine the dynamic characteristics of
the phase-locked loop. The capacitor must have very low leakage, therefore a high quality ceramic capacitor is
recommended. DO NOT use any type of polarized or electrolytic capacitor. Ceramic capacitors should have C0G or
NP0 dielectric. Avoid high-K dielectrics like Z5U and X7R; these and other ceramics which have piezoelectric
properties allow mechanical vibration in the system to increase the output jitter because the mechanical energy is
converted directly to voltage noise on the VCO input.
The values of the RC network determine the bandwidth of the PLL. The values of the loop filter components are
calculated using the constants K1 and K2 from the Loop Filter Constants table (page 7). The loop bandwidth is set
by the capacitor C and the constant K1 using the formula:
Parameter
Symbol
Conditions
Min.
Typ.
Max.
Units
Input Frequency
fIN
8.000
kHz
Output Clock Rise Time
tOR
0.8 to 2.0 V
1.5
ns
Output Clock Fall Time
tOF
2.0 to 0.8 V
1.5
ns
Output Clock Duty Cycle,
High time
tDC
At VDD/2
40
49 to 51
60
%
Absolute Clock Period
Jitter
1ns
Actual Mean Frequency
Error Versus Target (note
1)
Any clock selection
0
ppm
Parameter
Symbol
Conditions
Min.
Typ.
Max.
Units
Thermal Resistance Junction to
Ambient
θ
JA
Still air
120
°C/W
θ
JA
1 m/s air flow
115
°C/W
θ
JA
3 m/s air flow
105
°C/W
Thermal Resistance Junction to Case
θ
JC
58
°C/W
BW (Hz) =
C
K1
Equation 1
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