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參數(shù)資料
| 型號(hào)： | MK2069-01GILF |
| 廠商： | IDT, Integrated Device Technology Inc |
| 文件頁數(shù)： | 16/21頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC CLOCK SYNTHESIZER 56-TSSOP |
| 標(biāo)準(zhǔn)包裝： | 34 |
| 類型： | 時(shí)鐘同步器 |
| PLL： | 是 |
| 輸入： | LVCMOS |
| 輸出： | LVCMOS |
| 電路數(shù)： | 1 |
| 比率 - 輸入:輸出： | 3:3 |
| 差分 - 輸入:輸出： | 無/無 |
| 頻率 - 最大： | 160MHz |
| 除法器/乘法器： | 是/無 |
| 電源電壓： | 3.15 V ~ 3.45 V |
| 工作溫度： | -40°C ~ 85°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 56-TFSOP（0.240"，6.10mm 寬） |
| 供應(yīng)商設(shè)備封裝： | 56-TSSOP |
| 包裝： | 管件 |
| 產(chǎn)品目錄頁面： | 1254 (CN2011-ZH PDF) |
| 其它名稱： | 800-1782 800-1782-5 800-1782-ND |
MK2069-01
VCXO-BASED LINE CARD CLOCK SYNCHRONIZER
VCXO AND SYNTHESIZER
IDT VCXO-BASED LINE CARD CLOCK SYNCHRONIZER
4
MK2069-01
REV K 051310
Functional Description
The MK2069-01 is a PLL (phase locked loop) based clock
generator that generates output clocks synchronized to an
input reference clock. It contains two cascaded PLL’s with
user selectable divider ratios.
The first PLL is VCXO-based and uses an external pullable
crystal as part of the normal “VCO” (voltage controlled
oscillator) function of the PLL. The use of a VCXO assures
a low phase noise clock source even when a low PLL loop
bandwidth is implemented. A low loop bandwidth is needed
when the input reference frequency is low, or when jitter
attenuation of the input reference is desired.
The second PLL is used to translate or multiply the
frequency of the VCXO PLL which has a maximum output
frequency of 27 MHz. This second PLL, or Translator PLL,
uses an on-chip VCO circuit that can provide an output clock
up to 160 MHz. The Translator PLL uses a high loop
bandwidth (typically greater than 1 MHz) to assure stability
of the VCO clock output. It requires a stable, high frequency
input reference which is provided by the VCXO PLL.
The divide values of the divider blocks within both PLLs are
set by device pin configuration. This enables the system
designer to define the following:
Input clock frequency
VCXO crystal frequency
VCLK output frequency
RCLK output frequency, which is also the phase detector
frequency of the VCXO PLL.
TCLK output frequency
Any unused clock or logic outputs can be tri-stated to reduce
interference (jitter, phase noise) on other clock outputs.
Outputs can also be tri-stated for system testing purposes.
External components are used to configure the VCXO PLL
loop response. This serves to maximize loop stability and to
achieve the desired input clock jitter attenuation
characteristics.
42
VCLK
Output
Clock output from VCXO PLL
43
VDDP
Power
Power Supply connection for output drivers (VCLK, TCLK, RCLK, LD, LDR).
44
TCLK
Output
Clock output from Translator PLL
45
LD
Output
Lock detector output.
46
VDD
Power
Power Supply connection for digital circuitry.
47
OER
Input
Output enable for RCLK. RCLK is tri-stated when low (internal pull-up).
48
OEV
Input
Output enable for VCLK. VCLK is tri-stated when low (internal pull-up).
49
OET
Input
Output enable for TCLK. TCLK is tri-stated and the translator PLL is disabled
when low (internal pull-up).
50
OEL
Input
Output enable for LD and LDR. Both are tri-stated when low (internal pull-up).
51
ICLK1
Input
Reference clock input 1. 5V tolerant input.
52
MX0
Input
Input MUX selection bit 0 input (internal pull-up).
53
RV1
Input
Reference Divider bit 1 input, VCXO PLL (internal pull-up).
54
SV0
Input
Scaler Divider bit 0 input, VCXO PLL (internal pull-up).
55
SV1
Input
Scaler Divider bit 1 input, VCXO PLL (internal pull-up).
56
SV2
Input
Scaler Divider bit 2 input, VCXO PLL (internal pull-up).
Pin
Number
Pin
Name
Pin
Type
Pin Description
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| ICS87159AGLF | IC CLOCK GEN 1-8 LVCMOS 56-TSSOP |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| MK2069-01GILFTR | 功能描述:時(shí)鐘發(fā)生器及支持產(chǎn)品 VCXO-BASED LINE CARD CLOCK SYNCHRONIZER RoHS:否 制造商:Silicon Labs 類型:Clock Generators 最大輸入頻率:14.318 MHz 最大輸出頻率:166 MHz 輸出端數(shù)量:16 占空比 - 最大:55 % 工作電源電壓:3.3 V 工作電源電流:1 mA 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:QFN-56 |
| MK2069-01GITR | 功能描述:IC VCXO CLK SYNCHRONIZER 56TSSOP RoHS:否 類別:集成電路 (IC) >> 時(shí)鐘/計(jì)時(shí) - 時(shí)鐘發(fā)生器，PLL，頻率合成器 系列:- 標(biāo)準(zhǔn)包裝:39 系列:- 類型:* PLL:帶旁路 輸入:時(shí)鐘 輸出:時(shí)鐘 電路數(shù):1 比率 - 輸入:輸出:1:10 差分 - 輸入:輸出:是/是 頻率 - 最大:170MHz 除法器/乘法器:無/無 電源電壓:2.375 V ~ 3.465 V 工作溫度:0°C ~ 70°C 安裝類型:* 封裝/外殼:* 供應(yīng)商設(shè)備封裝:* 包裝:* |
| MK2069-03 | 制造商:ICS 制造商全稱:ICS 功能描述:VCXO-Based Clock Translator with High Multiplication |
| MK2069-03GI | 功能描述:IC VCXO CLK TRANSLATOR 56-TSSOP RoHS:否 類別:集成電路 (IC) >> 時(shí)鐘/計(jì)時(shí) - 時(shí)鐘發(fā)生器，PLL，頻率合成器 系列:- 標(biāo)準(zhǔn)包裝:27 系列:Precision Edge® 類型:頻率合成器 PLL:是 輸入:PECL，晶體 輸出:PECL 電路數(shù):1 比率 - 輸入:輸出:1:1 差分 - 輸入:輸出:無/是 頻率 - 最大:800MHz 除法器/乘法器:是/無 電源電壓:3.135 V ~ 5.25 V 工作溫度:0°C ~ 85°C 安裝類型:表面貼裝 封裝/外殼:28-SOIC（0.295"，7.50mm 寬） 供應(yīng)商設(shè)備封裝:28-SOIC 包裝:管件 |
| MK2069-03GITR | 功能描述:時(shí)鐘發(fā)生器及支持產(chǎn)品 VCXO-BASED CLOCK TRANSLATOR RoHS:否 制造商:Silicon Labs 類型:Clock Generators 最大輸入頻率:14.318 MHz 最大輸出頻率:166 MHz 輸出端數(shù)量:16 占空比 - 最大:55 % 工作電源電壓:3.3 V 工作電源電流:1 mA 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:QFN-56 |
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