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參數(shù)資料
| 型號： | MK2069-01GILF |
| 廠商： | IDT, Integrated Device Technology Inc |
| 文件頁數(shù)： | 18/21頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC CLOCK SYNTHESIZER 56-TSSOP |
| 標準包裝： | 34 |
| 類型： | 時鐘同步器 |
| PLL： | 是 |
| 輸入： | LVCMOS |
| 輸出： | LVCMOS |
| 電路數(shù)： | 1 |
| 比率 - 輸入:輸出： | 3:3 |
| 差分 - 輸入:輸出： | 無/無 |
| 頻率 - 最大： | 160MHz |
| 除法器/乘法器： | 是/無 |
| 電源電壓： | 3.15 V ~ 3.45 V |
| 工作溫度： | -40°C ~ 85°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 56-TFSOP（0.240"，6.10mm 寬） |
| 供應(yīng)商設(shè)備封裝： | 56-TSSOP |
| 包裝： | 管件 |
| 產(chǎn)品目錄頁面： | 1254 (CN2011-ZH PDF) |
| 其它名稱： | 800-1782 800-1782-5 800-1782-ND |
MK2069-01
VCXO-BASED LINE CARD CLOCK SYNCHRONIZER
VCXO AND SYNTHESIZER
IDT VCXO-BASED LINE CARD CLOCK SYNCHRONIZER
6
MK2069-01
REV K 051310
Setting TCLK Output Frequency
The clock frequency of TCLK is determined by:
Where:
FT Divider = 1 to 64
RT Divider = 1 to 4
The frequency range of TCLK is set by the operational range
of the internal VCO circuit and the output divider selections:
Where:
f(VCO) = 40 to 320 MHz
ST Divider = 2,4,8 or 16
A higher VCO frequency will generally produce lower phase
noise and therefore is preferred.
MK2069-01 Loop Response and JItter
Attenuation Characteristics
The MK2069-01 will reduce the transfer of phase jitter
existing on the input reference clock to the output clock. This
operation is known as jitter attenuation. The low-pass
frequency response of the VCXO PLL loop is the
mechanism that provides input jitter attenuation. Clock jitter,
more accurately called phase jitter, is the overall instability
of the clock period which can be measured in the time
domain using an oscilloscope, for instance. Jitter is
comprised of phase noise which can be represented in the
frequency domain. The phase noise of the input reference
clock is attenuated according to the VCXO PLL low-pass
frequency response curve. The response curve, and thus
the jitter attenuation characteristics, can be established
through the selection of external MK2069-01 passive
components and other device setting as explained in the
following section.
Setting the VCXO PLL Loop Response.
The VCXO PLL loop response is determined both by fixed
device characteristics and by other characterizes set by the
user. This includes the values of RS, CS, CP and RSET as
shown in the External VCXO PLL Components figure on this
page.
The VCXO PLL loop bandwidth is approximated by:
Where:
RS = Value of resistor RS in loop filter in Ohms
ICP = Charge pump current in amps
(see table on page 7)
KO = VCXO Gain in Hz/V
(see table on page 8)
SV Divider = 1,2,4,6,8,10,12 or 16
FV Divider = 1 to 4096
The above equation calculates the “normalized” loop
bandwidth (denoted as “NBW”) which is approximately
equal to the - 3dB bandwidth. NBW does not take into
account the effects of damping factor or the second pole
imposed by CP. It does, however, provide a useful
approximation of filter performance.
To prevent jitter on VCLK due to modulation of the VCXO
PLL by the phase detector frequency, the following general
rule should be observed:
.
The PLL loop damping factor is determined by:
Where:
CS = Value of capacitor CS in loop filter in Farads
f(TCLK)
FT Divider
RT Divider
----------------------------
f(VCLK)
×
=
f(TCLK)
f(VC0)
ST Divider
-----------------------
=
NBW(VCXO PLL)
R
S
I
CP
×
K
O
×
2
π SV Divider
×
FV Divider
×
-----------------------------------------------------------------------------
=
NBW(VCO PLL)
f(Phase Detector)
20
---------------------------------------
≤
DF(VCLK)
R
S
2
------
I
CP
C
S
×
K
O
×
SV Divider
FV Divider
×
---------------------------------------------------------------
×
=
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| MK2069-01GILFTR | 功能描述:時鐘發(fā)生器及支持產(chǎn)品 VCXO-BASED LINE CARD CLOCK SYNCHRONIZER RoHS:否 制造商:Silicon Labs 類型:Clock Generators 最大輸入頻率:14.318 MHz 最大輸出頻率:166 MHz 輸出端數(shù)量:16 占空比 - 最大:55 % 工作電源電壓:3.3 V 工作電源電流:1 mA 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:QFN-56 |
| MK2069-01GITR | 功能描述:IC VCXO CLK SYNCHRONIZER 56TSSOP RoHS:否 類別:集成電路 (IC) >> 時鐘/計時 - 時鐘發(fā)生器，PLL，頻率合成器 系列:- 標準包裝:39 系列:- 類型:* PLL:帶旁路 輸入:時鐘 輸出:時鐘 電路數(shù):1 比率 - 輸入:輸出:1:10 差分 - 輸入:輸出:是/是 頻率 - 最大:170MHz 除法器/乘法器:無/無 電源電壓:2.375 V ~ 3.465 V 工作溫度:0°C ~ 70°C 安裝類型:* 封裝/外殼:* 供應(yīng)商設(shè)備封裝:* 包裝:* |
| MK2069-03 | 制造商:ICS 制造商全稱:ICS 功能描述:VCXO-Based Clock Translator with High Multiplication |
| MK2069-03GI | 功能描述:IC VCXO CLK TRANSLATOR 56-TSSOP RoHS:否 類別:集成電路 (IC) >> 時鐘/計時 - 時鐘發(fā)生器，PLL，頻率合成器 系列:- 標準包裝:27 系列:Precision Edge® 類型:頻率合成器 PLL:是 輸入:PECL，晶體 輸出:PECL 電路數(shù):1 比率 - 輸入:輸出:1:1 差分 - 輸入:輸出:無/是 頻率 - 最大:800MHz 除法器/乘法器:是/無 電源電壓:3.135 V ~ 5.25 V 工作溫度:0°C ~ 85°C 安裝類型:表面貼裝 封裝/外殼:28-SOIC（0.295"，7.50mm 寬） 供應(yīng)商設(shè)備封裝:28-SOIC 包裝:管件 |
| MK2069-03GITR | 功能描述:時鐘發(fā)生器及支持產(chǎn)品 VCXO-BASED CLOCK TRANSLATOR RoHS:否 制造商:Silicon Labs 類型:Clock Generators 最大輸入頻率:14.318 MHz 最大輸出頻率:166 MHz 輸出端數(shù)量:16 占空比 - 最大:55 % 工作電源電壓:3.3 V 工作電源電流:1 mA 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:QFN-56 |
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