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參數資料
| 型號： | MK2069-01GILF |
| 廠商： | IDT, Integrated Device Technology Inc |
| 文件頁數： | 3/21頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC CLOCK SYNTHESIZER 56-TSSOP |
| 標準包裝： | 34 |
| 類型： | 時鐘同步器 |
| PLL： | 是 |
| 輸入： | LVCMOS |
| 輸出： | LVCMOS |
| 電路數： | 1 |
| 比率 - 輸入:輸出： | 3:3 |
| 差分 - 輸入:輸出： | 無/無 |
| 頻率 - 最大： | 160MHz |
| 除法器/乘法器： | 是/無 |
| 電源電壓： | 3.15 V ~ 3.45 V |
| 工作溫度： | -40°C ~ 85°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 56-TFSOP（0.240"，6.10mm 寬） |
| 供應商設備封裝： | 56-TSSOP |
| 包裝： | 管件 |
| 產品目錄頁面： | 1254 (CN2011-ZH PDF) |
| 其它名稱： | 800-1782 800-1782-5 800-1782-ND |
MK2069-01
VCXO-BASED LINE CARD CLOCK SYNCHRONIZER
VCXO AND SYNTHESIZER
IDT VCXO-BASED LINE CARD CLOCK SYNCHRONIZER
11
MK2069-01
REV K 051310
Lock Detection Circuit Diagram
If the lock detection circuit is not used, the LDR output may
remain unconnected, however the LDC input should be tied
high or low. If the PCB was designed to accommodate the
RLD and CLD components but the LD output will not be
used, RLD can remain unstuffed and CLD can be replaced
with a resistor (< 10 kohm).
Power Supply Considerations
As with any integrated clock device, the MK2069-01 has a
special set of power supply requirements:
The feed from the system power supply must be filtered
for noise that can cause output clock jitter. Power supply
noise sources include the system switching power supply
or other system components. The noise can interfere with
device PLL components such as the VCO or phase
detector.
Each VDD pin must be decoupled individually to prevent
power supply noise generated by one device circuit block
from interfering with another circuit block.
Clock noise from device VDD pins must not get onto the
PCB power plane or system EMI problems may result.
This above set of requirements is served by the circuit
illustrated in the Recommended Power Supply Connection
(next page). The main features of this circuit are as follows:
Only one connection is made to the PCB power plane.
The capacitors and ferrite chip (or ferrite bead) on the
common device supply form a lowpass ‘pi’ filter that
remove noise from the power supply as well as clock
noise back toward the supply. The bulk capacitor should
be a tantalum type, 1
μF minimum. The other capacitors
should be ceramic type.
The power supply traces to the individual VDD pins
should fan out at the common supply filter to reduce
interaction between the device circuit blocks.
The decoupling capacitors at the VDD pins should be
ceramic type and should be as close to the VDD pin as
possible. There should be no via’s between the
decoupling capacitor and the supply pin.
Recommended Power Supply Connection
Series Termination Resistor
Output clock PCB traces over 1 inch should use series
termination to maintain clock signal integrity and to reduce
EMI. To series terminate a 50
Ω trace, which is a commonly
used PCB trace impedance, place a 33
Ω resistor in series
with the clock line as close to the clock output pin as
possible. The nominal impedance of the clock output is 20
Ω.
Lo c k D e te c tio n C irc uit
Lo c k
Q u a lific a tio n
C ounte r
(8 up , 1 dow n)
VC XO
Ph a s e
De te c to r
Erro r
Ou tp u t
LD
LD C
LD R
RL D
CL D
R ESET
FV
Div id e r
Ou tp u t
OE L
Input Th re s hold
s e t to V D D /2
Connection Via to 3.3V
Power Plane
Ferrite
Chip
0.
1
F
BU
L
K
1
nF
VDD
Pin
0.
01
F
VDD
Pin
0.
0
1
F
VDD
Pin
0.
01
F
VDD
Pin
0.
01
F
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相關代理商/技術參數 |
參數描述 |
|---|---|
| MK2069-01GILFTR | 功能描述:時鐘發(fā)生器及支持產品 VCXO-BASED LINE CARD CLOCK SYNCHRONIZER RoHS:否 制造商:Silicon Labs 類型:Clock Generators 最大輸入頻率:14.318 MHz 最大輸出頻率:166 MHz 輸出端數量:16 占空比 - 最大:55 % 工作電源電壓:3.3 V 工作電源電流:1 mA 最大工作溫度:+ 85 C 安裝風格:SMD/SMT 封裝 / 箱體:QFN-56 |
| MK2069-01GITR | 功能描述:IC VCXO CLK SYNCHRONIZER 56TSSOP RoHS:否 類別:集成電路 (IC) >> 時鐘/計時 - 時鐘發(fā)生器，PLL，頻率合成器 系列:- 標準包裝:39 系列:- 類型:* PLL:帶旁路 輸入:時鐘 輸出:時鐘 電路數:1 比率 - 輸入:輸出:1:10 差分 - 輸入:輸出:是/是 頻率 - 最大:170MHz 除法器/乘法器:無/無 電源電壓:2.375 V ~ 3.465 V 工作溫度:0°C ~ 70°C 安裝類型:* 封裝/外殼:* 供應商設備封裝:* 包裝:* |
| MK2069-03 | 制造商:ICS 制造商全稱:ICS 功能描述:VCXO-Based Clock Translator with High Multiplication |
| MK2069-03GI | 功能描述:IC VCXO CLK TRANSLATOR 56-TSSOP RoHS:否 類別:集成電路 (IC) >> 時鐘/計時 - 時鐘發(fā)生器，PLL，頻率合成器 系列:- 標準包裝:27 系列:Precision Edge® 類型:頻率合成器 PLL:是 輸入:PECL，晶體 輸出:PECL 電路數:1 比率 - 輸入:輸出:1:1 差分 - 輸入:輸出:無/是 頻率 - 最大:800MHz 除法器/乘法器:是/無 電源電壓:3.135 V ~ 5.25 V 工作溫度:0°C ~ 85°C 安裝類型:表面貼裝 封裝/外殼:28-SOIC（0.295"，7.50mm 寬） 供應商設備封裝:28-SOIC 包裝:管件 |
| MK2069-03GITR | 功能描述:時鐘發(fā)生器及支持產品 VCXO-BASED CLOCK TRANSLATOR RoHS:否 制造商:Silicon Labs 類型:Clock Generators 最大輸入頻率:14.318 MHz 最大輸出頻率:166 MHz 輸出端數量:16 占空比 - 最大:55 % 工作電源電壓:3.3 V 工作電源電流:1 mA 最大工作溫度:+ 85 C 安裝風格:SMD/SMT 封裝 / 箱體:QFN-56 |
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