參數(shù)資料
型號: MK40X512VMD100
廠商: FREESCALE SEMICONDUCTOR INC
元件分類: 微控制器/微處理器
英文描述: RISC MICROCONTROLLER, PBGA144
封裝: 13 X 13 MM, MAPBGA-144
文件頁數(shù): 28/68頁
文件大?。?/td> 1005K
代理商: MK40X512VMD100
Table 21. EzPort switching specifications (continued)
Num
Description
Min.
Max.
Unit
EP1
EZP_CK frequency of operation (all commands except
READ)
fSYS/2
MHz
EP1a
EZP_CK frequency of operation (READ command)
fSYS/8
MHz
EP2
EZP_CS negation to next EZP_CS assertion
2 x tEZP_CK
ns
EP3
EZP_CS input valid to EZP_CK high (setup)
5
ns
EP4
EZP_CK high to EZP_CS input invalid (hold)
5
ns
EP5
EZP_D input valid to EZP_CK high (setup)
2
ns
EP6
EZP_CK high to EZP_D input invalid (hold)
5
ns
EP7
EZP_CK low to EZP_Q output valid (setup)
12
ns
EP8
EZP_CK low to EZP_Q output invalid (hold)
0
ns
EP9
EZP_CS negation to EZP_Q tri-state
12
ns
EP2
EP3
EP4
EP5
EP6
EP7
EP8
EP9
EZP_CK
EZP_CS
EZP_Q (output)
EZP_D (input)
Figure 10. EzPort Timing Diagram
6.4.3 Flexbus Switching Specifications
All processor bus timings are synchronous; input setup/hold and output delay are given in
respect to the rising edge of a reference clock, FB_CLK. The FB_CLK frequency may be
the same as the internal system bus frequency or an integer divider of that frequency.
Peripheral operating requirements and behaviors
K40 Sub-Family Data Sheet Data Sheet, Rev. 1, 11/2010.
34
Preliminary
Freescale Semiconductor, Inc.
Preliminary
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