參數(shù)資料
型號: MK40X512VMD100
廠商: FREESCALE SEMICONDUCTOR INC
元件分類: 微控制器/微處理器
英文描述: RISC MICROCONTROLLER, PBGA144
封裝: 13 X 13 MM, MAPBGA-144
文件頁數(shù): 50/68頁
文件大?。?/td> 1005K
代理商: MK40X512VMD100
Table 39. Slave Mode DSPI Timing (High-speed mode) (continued)
Num
Description
Min.
Max.
Unit
DS12
DSPI_SCK to DSPI_SOUT invalid
0
ns
DS13
DSPI_SIN to DSPI_SCK input setup
2
ns
DS14
DSPI_SCK to DSIP_SIN input hold
7
ns
DS15
DSPI_SS active to DSPI_SOUT driven
14
ns
DS16
DSPI_SS inactive to DSPI_SOUT not driven
14
ns
First data
Last data
First data
Data
Last data
Data
DS15
DS10
DS9
DS16
DS11
DS12
DS14
DS13
DSPI_SS
DSPI_SCK
(CPOL=0)
DSPI_SOUT
DSPI_SIN
Figure 21. DSPI Classic SPI Timing — Slave Mode
6.8.6 SDHC Specifications
The following timing specs are defined at the chip I/O pin and must be translated
appropriately to arrive at timing specs/constraints for the physical interface.
Table 40. SDHC switching specifications
Num
Symbol
Description
Min.
Max.
Unit
Card input clock
SD1
fpp
Clock frequency (low speed)
0
400
kHz
fpp
Clock frequency (SD\SDIO full speed)
0
25
MHz
fpp
Clock frequency (MMC full speed)
0
20
MHz
fOD
Clock frequency (identification mode)
0
400
kHz
SD2
tWL
Clock low time
7
ns
SD3
tWH
Clock high time
7
ns
SD4
tTLH
Clock rise time
3
ns
SD5
tTHL
Clock fall time
3
ns
SDHC output / card inputs SDHC_CMD, SDHC_DAT (reference to SDHC_CLK)
Table continues on the next page...
Peripheral operating requirements and behaviors
K40 Sub-Family Data Sheet Data Sheet, Rev. 1, 11/2010.
54
Preliminary
Freescale Semiconductor, Inc.
Preliminary
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