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參數(shù)資料
| 型號： | MK5027 |
| 廠商： | 意法半導體 |
| 英文描述： | SS7 SIGNALLING LINK CONTROLLER |
| 中文描述： | 七號信令鏈路控制器 |
| 文件頁數(shù)： | 3/19頁 |
| 文件大?。?/td> | 183K |
| 代理商： | MK5027 |
Table 1:
PinDescription (continued)
Signal Name
BM1
BUSAKO
Pin(s)
16
Type
O/3S
Descriplion
Pins 15 and 16 are programmable though bit 00 of CSR4 (BCON).
If CSR4<00> BCON = 0,
I/O PIN 15 = BMO (O/3S)
I/O PIN 16 = BM1 (O/3S)
BYTE MASK<1:0> indicates the byte(s) on the DAL to be read or written
during this bus transaction. MK5027 drives these lines only as a Bus
Master. MK5027 ignores the BM lines when it is a Bus Slave.
Byte selection is done as outlined in the following table.
BM1
BM0
TYPE OF TRANSFER
LOW
LOW
HIGH
HIGH
If CSR4<00>BCON = 1,
I/O PIN 15 = BYTE (O/3S)
I/O PIN 16 = BUSAKO(O)
Byte selection is done using the BYTE line and DAL<00> latched during
the address portion of the bus transaction. MK5027 drives BYTE only a
Bus Master and ignores it when a Bus Slave. Byte selectionis done as
outlined in the following table.
LOW
HIGH
LOW
HIGH
ENTIRE WORD
UPPER BYTE (DAL<15:08>)
LOWER BYTE (DAL<07:00>)
NONE
BYTE
DAL<00>
TYPE OF TRANSFER
LOW
LOW
HIGH
HIGH
LOW
HIGH
LOW
HIGH
ENTIRE WORD
ILLEGAL CONDITION
LOWER BYTE
UPPER BYTE
BUSAKOis a bus request daisy chain output. If MK5027 is not requesting
the bus and it receives HLDA, BUSAKOwill be driven low. If MK5027 is
requesting the bus when it receives HLDA,BUSAKOwill remain high.
Note: All transfers are entire word unless the MK5027 is configured for 8
bit operation.
Pins 17 is configured through bit 0of CSR4.
If CSR4<00> BCON = 0,
I/O PIN 17 = HOLD
HOLDrequest is asserted by MK5027 when it requires a DMA cycle, if
HLDA is inactive, regardless of the previous state of the HOLD pin.
HOLDis held low for the entire ensuing bus transaction.
If CSR4<00> BCON = 1,
I/O PIN 17 = BUSRQ
BUSRQ is asserted by MK5027 when it requires a DMA cycle if the prior
state of the BUSRQ pin was high and HLDA is inactive. BUSRQ is held
low for the entire ensuing bus transaction.
The active level of ADDRESS STROBE is programmable through CSR4.
The address portion of a bus transfer occurs while this signal is at its
asserted level. This signal is driven by MK5027 while it is the BUS
MASTER. At all other times, the signal is tristated.
If CSR4<01> ACON = 0,
I/O PIN 18 = ALE
ADDRESS LATCH ENABLE isused to demultiplex the DALlines and define
the address portion of the transferand remains low during the data portion.
If CSR4<01> ACON = 1,
I/O PIN 18 = AS
As AS, the signalpulses lowduring the address portion of the bus
transfer. The low to high transition of AScan be used by a slave device to
strobe the address into aregister.
ASis effectively the inversion of ALE.
HOLDAKNOWLEDGEistheresponse toHOLD. WhenHLDAis low inresponse
toMK5027’s assertion ofHOLD, theMK5027 istheBus Master. HLDAshould be
desasserted ONLY afterHOLDhas beenreleased bytheMK5027.
HOLD
BUSRQ
17
IO/OD
ALE
AS
18
O/3S
HLDA
19
I
MK5027
3/19
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