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參數(shù)資料
| 型號： | MK5027 |
| 廠商： | 意法半導體 |
| 英文描述： | SS7 SIGNALLING LINK CONTROLLER |
| 中文描述： | 七號信令鏈路控制器 |
| 文件頁數(shù)： | 4/19頁 |
| 文件大?。?/td> | 183K |
| 代理商： | MK5027 |
Table 1:
PinDescription (continued)
Signal Name
CS
Pin(s)
20
Type
I
Descriplion
CHIP SELECT indicates, when low, that the MK5027 is the slave device
for the data transfer.CS must be valid througout the enture transaction.
ADDRESS selects the Register Address Port orthe Register Data Port. It
must be valid throughout the data portion of the transfer and is only used
by the chip when CS is low.
ADR
21
I
ADR
LOW
HIGH
When the MK5027 isa Bus Master, READY is an asynchronous
acknowledgement from the bus memory that memory will accept data in a
WRITE cycle or that memory has put data on the DAL lines in a READ
cycle.
As a bus Slave, the MK5027 asserts READY when it hasput data on the
DAL lines during a READ cycle oris about to take datafrom the DAL lines
during WRITE cycle. READY is a response to DAS and it will be released
after DASor CS is negated.
RESET is the Bus signal that will cause MK5027 to cease operation, clear
its internal logic and enter an idle state with the Power Off bit of CSR0 set.
TRANSMIT CLOCK. A 1x clock input for transmitter timing. TD changes
on the falling edge of TCLK.The frequency of TCLK may not be greater
than the frequency of SYSCLK.
DATA TERMINAL READY, REQUEST TO SEND. Modem controlpin. Pin
26 is configurable through CSR5. This pin can be programmed to behave
as output RTS or as programmable IO pin DTR. If configured as RTS, the
MK5027 will assert this pin if it has data to send and throughout the
transmission of a signal unit.
RECEIVE CLOCK. A 1x clock input for receiver timing. RD is sampled on
the rising edge of RCLK. The frequency of RCLK may not be greater than
the frequency of SYSCLK.
SYSTEM CLOCK. System clock used for internaltiming of the MK5027.
SYSCLK should be a square wave, of frequency up to 10MHz.
TRANSMIT DATA. Transmit serial dataoutput.
DATA SET READY, CLEAR TO SEND. Modem Control Pin. Pin 30 is
configurable through CSR5. This pin can be programmed to behave as
input CTS or as programmable IO pin DSR. If configured as CTS, the
MK5027 will transmit allones while CTS is high.
RECEIVE DATA. Received serial data input.
Address bits <23:16> used in conjunction with DAL <15:00> to produce a
24 bit address. MK5027 drives these lines only as a Bus Master.
A23-A20 may be driven continuously as described in the CSR4<7> BAEN
bit.
Ground Pins
Power Supply Pin
+5.0 VDC
±
5%
PORT
REGISTER DATA PORT
REGISTER ADDRESS PORT
READY
22
IO/OD
RESET
23
I
TCLK
25
I
DTR
RTS
26
IO
RCLK
27
I
SYSCLK
28
I
TD
DSR
CTS
29
30
O
IO
RD
31
I
A<23:16>
32-39
O/3S
VSS-GND
VCC
1, 24
48
MK5027
4/19
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