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參數(shù)資料
| 型號(hào)： | MK74ZD133YT |
| 英文描述： | PLL and 32-Output Clock Driver |
| 中文描述： | PLL和32個(gè)輸出時(shí)鐘驅(qū)動(dòng)器 |
| 文件頁(yè)數(shù)： | 1/8頁(yè) |
| 文件大?。?/td> | 116K |
| 代理商： | MK74ZD133YT |
MK74ZD133
PLL and 32-Output Clock Driver
PRELIMINARY INFORMAT ION
MDS 74ZD133 C
Integrated Circuit Systems, Inc.525 Race StreetSan JoseCA95126(408)295-9800telwww.icst.com
1
Revision 010899
Printed 11/17/00
56 pin SSOP or 64 pin LQFP package
On-chip PLL generates output clocks up to
80 MHz (SSOP) or 133.33 MHz (LQFP)
Zero delay plus multiplier function
32 low-skew outputs can eliminate chip-to-chip
skew concerns in systems with less than 33 clocks
Output to output skew of 200 ps (with stagger)
Device to device skew of 700ps
Staggered, fixed skew helps reduce EMI
Tri-state (Output Enable) pin
Output blocks can be independently powered off
250 ps typical fixed delay between input and
output in “Multiplier” mode
Ideal for Fast Ethernet and Gigabit Ethernet
designs
Good for video servers
3.3V±5% supply voltage
The MK74ZD133 is a monolithic CMOS high
speed clock driver that includes an on-chip PLL
(Phase Locked Loop). Ideal for communications
and other systems that require a large number of
high-speed clocks, the unique combination of PLL
and 32 outputs can eliminate oscillators and
multiple low skew buffers. With 32 outputs
included in one device, there is also no need to
worry about chip-to-chip skew. The zero delay
modes cause the input clock rising edge to be
synchronized with all of the outputs’ rising edges.
The MK74ZD133 has a large selection of built-in
multipliers, making it possible to run from a clock
input as low as 10 MHz and generate high
frequency outputs up to 80 MHz in the SSOP. For
speeds up to 133.33 MHz, use the LQFP package.
Block Diagram
Description
Features
Input
Buffer
Clock
Synthesis
Circuitry
Output
Buffer
Output
Buffer
Output 2
Output 1
Output
Buffer
5
S4:0
Clock input
Output 32
OE (all outputs)
VDD
GND
FBIN
Output
Buffer
Output 3
Optional External Connection to Output 3 (for Zero Delay Mode)
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