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參數(shù)資料
| 型號(hào)： | MK74ZD133YT |
| 英文描述： | PLL and 32-Output Clock Driver |
| 中文描述： | PLL和32個(gè)輸出時(shí)鐘驅(qū)動(dòng)器 |
| 文件頁(yè)數(shù)： | 4/8頁(yè) |
| 文件大小： | 116K |
| 代理商： | MK74ZD133YT |
MK74ZD133
PLL and 32-Output Clock Driver
PRELIMINARY INFORMAT ION
MDS 74ZD133 C
Integrated Circuit Systems, Inc.525 Race StreetSan JoseCA95126(408)295-9800telwww.icst.com
4
Revision 010899
Printed 11/17/00
Number
1
2, 56, 57
Name
FBOUT3
OUT4, 1, and 2
GND
OUT5-OUT8
VDD5:8
OUT9-OUT12
VDD9:12
VDD13:14
OE (see note)
DC
OUT13-OUT14
VDD
Type
O
O
P
O
P
O
P
P
I
-
O
P
O
P
O
P
O
I/O
P
I/O
I/O
I/O
I/O
I
I
Description
Clock output 3. Connect to pin 61 FBIN for Zero Delay Mode.
Clock outputs 4, 1 and 2 respectively.
Connect to ground.
Clock outputs 5 through 8; level set by VDD5:8 on pin 6.
Power supply for outputs 5 through 8. Cannot exceed VDD.
Clock outputs 9 through 12; level set by VDD9:12 on pin 12.
Power supply for outputs 9 through 12. Cannot exceed VDD.
Power supply for outputs 13 and 14. Cannot exceed VDD.
Output Enable. Tri-states all clock outputs when low. Internal pull-up.
Don't Connect. Do not connect anything to these pins.
Clock outputs 13 and 14; level set by VDD13:14 on pin 16.
Power supply for internal circuits and OUT1:4, OUT15:20, and OUT25:32.
Clock outputs 15 through 20.
Connect to ground.
Clock outputs 21 through 24; level set by VDD21:24 on pin 40.
Power supply for outputs 21 through 24. Cannot exceed VDD.
Clock outputs 25 through 27.
Clock output 28 and output frequency select 0 per table on page 5.
Power supply for internal circuits and OUT1:4, OUT15:20, and OUT25:32.
Clock output 29 and output frequency select 1 per table on page 5.
Clock output 30 and output frequency select 2 per table on page 5.
Clock output 31 and output frequency select 3 per table on page 5.
Clock output 32 and output frequency select 4 per table on page 5.
Clock input for reference.
Feedback input for "zero delay" in Multiplier Mode.
3, 9, 15, 21, 30, 32
4, 5, 7, 8
6
10, 11, 13, 14
12
16
17
18, 22, 23, 31
19, 20
24, 25, 33, 34
26, 27, 28, 29, 35, 36 OUT15-OUT20
37, 43, 49, 50, 58, 59
38, 39, 41, 42
40
44, 45, 46
47
48, 54, 62, 63, 64
51
52
53
55
60
61
Type: I = Input, O = output, P = power supply connection, I/O=input upon power up, becoming an output clock within 10 ms later.
GND
OUT21-OUT24
VDD21:24
OUT25-OUT27
OUT28/S0
VDD
OUT29/S1
OUT30/S2
OUT31/S3
OUT32/S4
CLKIN
FBIN
Pin Descriptions for 64 pin LQFP (Y package)
Important Note for OE functionality:
To use the output enable function, once the OE has been taken low,
and the outputs have been tri-stated, the VDD must be removed and reapplied for the clocks to run again.
Staggered output skews for 64 pin LQFP (Y)
To aid in the reduction of EMI, and to allow the board
designer the flexibility of running different length traces whose clock edges will still line up at their
destinations, the MK74ZD133Y comes with different fixed skews for different outputs. All skews are with
respect to OUT1 (pin 56), and are measured into 33
termination resistors with 15 pF capacitive loads.
Output Name
OUT1, OUT25:32
OUT2,3, OUT5:14, OUT23,24
OUT4, OUT15:22
Pin Numbers
Typical Skew
0
- 150 ps
- 300 ps
Maximum variation
200 ps
200 ps
200 ps
56, 44, 45, 46, 47, 51, 52, 53, 55
57, 1, 4, 5, 7, 8,10,11,13,14, 19,20,41,42
2, 26, 27, 28, 29, 35, 36, 38, 39
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