ML2724
PIN
SIGNAL
NAME
I/O
FUNCTION
DIAGRAM
SERIAL BUS SIGNALS
4
EN
I (CMOS)
Control Bus Enable. Enable pin for the
three-wire serial control bus that sets the
operating frequency and programmable
options. The control registers are loaded
on a low-to-high transition of the signal.
Serial control bus data is ignored when
this signal is high. This is a CMOS input,
and the thresholds are referenced to
VDD and VSS.
5
DATA
I (CMOS)
Serial Control Bus Data. 16-bit words,
which include programming data and the
two-bit address of a control, register. This
is a CMOS input, and the thresholds are
referenced to VDD and VSS.
6
CLK
I (CMOS)
Serial control bus data is clocked in on
the rising edge when EN is low. This is a
CMOS input; the thresholds are
referenced to VDD and VSS.
31
VSS
VDD
5.5k
4
EN
8
1.7p
5
DATA
6
CLK
FUNCTIONAL DESCRIPTION
The ML2724 is a fully integrated 1.5Mbps frequency shift keyed (FSK) transceiver that operates in the unlicensed
2.4GHz ISM frequency band. The device has been optimized for digital cordless telephone applications and includes all
the frequency generation, receive and transmit functions for a raw data rate of 1.5Mbps. This high data rate allows for
data spreading, such as Direct Sequence Spread Spectrum (DSSS) modulation, which improves range. The ML2724
receiver architecture is a dual conversion Low IF, which has all of the sensitivity and selectivity advantages of a
traditional super-heterodyne receiver without requiring costly, bulky external filters.
Filter
Alignment
PLL
Divider
TXO/TXOB
2.4 GHz
Output
Quadrature
Downmixers
Quadrature
Divider
1.6 GHz
VCO
PLL Loop
Filter
DOUT
Receive Data
Out
DIN
Transmit Data In
Ref.
Divider
Control
Registers
Serial
Control Bus
RSSI
P.D.
FREF
Frequency
Reference
Mode
Control
Parallel
control lines
Divide
by 2
Two-port
Modulator
F
to
V
RSSI
RXI
2.4 GHz
Receive Input
Test Mux
TPC
PAON
RXON
XCEN
DATA
CLK
EN
VTUNE
QPO
Transmit
Mixer
Bandgap
2
AOUT
Figure 2: ML2724 Internal Block Diagram
DS2724-F-01
FINAL DATASHEET
APRIL 2003
12