參數(shù)資料
型號: ML2724DH
英文描述: 2.4GHz Low-IF 1.5Mbps FSK Transceiver Final Datasheet
中文描述: 2.4GHz的低IF 1.5Mbps的FSK收發(fā)器最終數(shù)據(jù)表
文件頁數(shù): 18/26頁
文件大?。?/td> 864K
代理商: ML2724DH
ML2724
NAME
DESCRIPTION
DEFINITION
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Set all bits to 0 (zero)
RCLP
RSSI Clip Disable
0: RSSI clipped to 1.9V at –15dBm
1: RSSI not clipped
LVLO
Low Voltage Lockout
0: PAON Undisturbed
1: PAON De-asserted for VCCA<2.65V. Reset on RXON high
Reserved
Reserved
Set to 0
TXM
TX RF Output Mode
0: TX RF Output always on in TX mode
1: TX RF Output follows PAON signal
TPC
Transmit Power Control
0: AOUT pin pulled to ground
1: AOUT pin high impedance
TXCW
Transmit Test Mode
0: FSK modulation in Transmit mode
1: CW (no modulation in Transmit mode)
Reserved
Reserved
Set to 0
AOUT
Analog Output
0: AOUT pin is Transmit Power Control
1: AOUT pin is Analog Data Out
RD0
Reference Frequency Select
0: 6.144MHz nominal reference frequency
1: 12.288MHz nominal reference frequency (preferred)
QPP
PLL Charge Pump Polarity
0: For fc < fref, charge pump sources current
1: For fc < fref, charge pump sinks current
ADR1
MSB Address Bit
ADR1=0
ADR0
LSB Address Bit
ADR0=0
Table 3: Register 0 -- PLL Configuration Register
NAME
DESCRIPTION
DEFINITION
Reserved
Reserved
Set all bits to 0 (zero)
CHQ11
CHQ10
CHQ9
CHQ8
CHQ7
CHQ6
CHQ5
CHQ4
CHQ3
CHQ2
CHQ1
CHQ0
Channel Frequency select bits
Divide ratio=f
c
/1.024
ADR1
MSB Address Bit
ADR1=0
ADR0
LSB Address Bit
ADR0=1
Table 4: Register 1 – Channel Frequency Register
DS2724-F-01
FINAL DATASHEET
APRIL 2003
18
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