參數(shù)資料
型號(hào): ML2724DH
英文描述: 2.4GHz Low-IF 1.5Mbps FSK Transceiver Final Datasheet
中文描述: 2.4GHz的低IF 1.5Mbps的FSK收發(fā)器最終數(shù)據(jù)表
文件頁(yè)數(shù): 6/26頁(yè)
文件大?。?/td> 864K
代理商: ML2724DH
ML2724
SYMBOL
PARAMETER
CONDITIONS
MIN
TYP
MAX
UNITS
V
RSMN
RSSI minimum voltage
No signal into RXI
75
mV
V
RSMXC
RSSI maximum voltage (clipped)
-10 dBm into RXI
1.6
1.95
V
TRANSMIT RF MIXER
P
OSE
Output power, single ended
TRXO or TRXOB, f
C
=2.445 GHz
-3
1
5
dBm
P
ODIF
Output power, differential
P
(TRXO,TRXOB)
, f
C
=2.445 GHz
-1
3
6
dBm
Z
OUT
Output impedance
TRXO or TRXOB, f
C
=2.445 GHz
12+j0
TRANSMIT MODULATION
f
DEV
Modulation Deviation, @2.4GHz
200us of consecutive ‘1’s or ‘0’s
500
512
524
kHz
f
OS
Modulation center frequency
offset
50us after RXON low
-50
+50
kHz
TRANSMIT DATA FILTER
BW
TX
Transmit Data Filter Bandwidth
3dB Bandwidth
1.4
MHz
TX spurious
Image
-25
-20
dBc
dBc
INTERFACE LOGIC LEVELS
INPUTS (DIN, XCEN, RXON, DATA, CLK, EN)
V
IH
Input high voltage
(never exceed VDD)
0.75*VDD
VDD
V
V
IL
Input low voltage
0
0.25*VDD
V
I
B
Input bias current
-5
0
5
μ
A
C
IN
Input capacitance
(measured at 1MHz)
4
pF
OUTPUTS (DOUT, PAON)
V
OH
DOUT high voltage
I
o
=0.1mA
VDD-0.4
V
V
OL
DOUT low voltage
I
o
=-0.1mA
0.4
V
I
o
DOUT sink/source current
0.1
mA
V
OH
PAON output high voltage
Sourcing 0.5 mA
VDD-0.4
V
V
OL
PAON output low voltage
Sinking 0.5 mA
0.4
V
I
o
PAON source/sink current
0.5
mA
3 WIRE SERIAL BUS TIMING
t
r
CLK input rise time
15
ns
t
f
CLK input fall time
15
ns
t
ck
CLK period
50
ns
t
ew
CLK pulse width
100
ns
t
l
Delay from last CLK falling edge
15
ns
t
se
EN setup time to ignore next
rising CLK
15
ns
t
s
DATA-to-CLK setup time
15
ns
t
h
DATA-to-CLK hold time
See Figure 4
15
ns
DS2724-F-01
FINAL DATASHEET
APRIL 2003
6
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