
ML4841
REV. 1.0 10/12/2000
9
FUNCTIONAL DESCRIPTION
(Continued)
dictates the proper compensation of the two
transconductance error amplifiers. Figure 3 shows the
types of compensation networks most commonly used for
the voltage and current error amplifiers, along with their
respective return points. The current loop compensation is
returned to V
REF
to produce a soft-start characteristic on
the PFC: as the reference voltage comes up from zero
volts, it creates a differentiated voltage on IEAO which
prevents the PFC from immediately demanding a full duty
cycle on its boost converter.
There are two major concerns when compensating the
voltage loop error amplifier; stability and transient
response. Optimizing interaction between transient
response and stability requires that the error amplifier’s
open-loop crossover frequency should be 1/2 that of the
line frequency, or 23Hz for a 47Hz line (lowest
anticipated international power frequency). The gain vs.
input voltage of the ML4841’s voltage error amplifier has
a specially shaped nonlinearity such that under steady-
state operating conditions the transconductance of the
error amplifier is at a local minimum. Rapid perturbations
in line or load conditions will cause the input to the
voltage error amplifier (V
FB
) to deviate from its 2.5V
(nominal) value. If this happens, the transconductance of
the voltage error amplifier will increase significantly, as
shown in the Typical Performance Characteristics. This
increases the gain-bandwidth product of the voltage loop,
resulting in a much more rapid voltage loop response to
such perturbations than would occur with a conventional
linear gain characteristic.
The current amplifier compensation is similar to that of
the voltage error amplifier with the exception of the
choice of crossover frequency. The crossover frequency of
the current amplifier should be at least 10 times that of
the voltage amplifier, to prevent interaction with the
voltage loop. It should also be limited to less than 1/6th
that of the switching frequency, e.g. 16.7kHz for a
100kHz switching frequency.
For more information on compensating the current and
voltage control loops, see Application Notes 33 and 34.
Application Note 16 also contains valuable information
for the design of this class of PFC.
Oscillator (RAMP 1)
The oscillator frequency is determined by the values Of
R
T
and C
T
, which determine the ramp and off-time of the
oscillator output clock:
f
t
t
OSC
RAMP
DISCHARGE
=
+
1
(2)
The deadtime of the oscillator is derived from the
following equation:
t
C
R
InV
V
RAMP
T
T
REF
REF
=
×
×
1 25
3 75
.
.
(3)
at V
REF
= 7.5V:
t
C
R
RAMP
T
T
=
×
×
0 51
.
The ramp of the oscillator may be determined using:
t
V
mA
C
C
DISCHARGE
T
T
=
×
=
×
2 5
5 1
.
490
.
(4)
The deadtime is so small (t
RAMP
>> t
DEADTIME
) that the
operating frequency can typically be approximated by:
f
t
OSC
RAMP
=
1
(5)
EXAMPLE:
For the application circuit shown in the data sheet, with
the oscillator running at:
f
kHz
t
OSC
RAMP
=
=
200
1
t
R
C
RAMP
T
T
=
×
×
= ×
6
0 51
.
Solving for R
T
x C
T
yields 2 x 10
-4
. Selecting standard
components values, C
T
= 470pF, and R
T
= 41.2k
.
The deadtime of the oscillator adds to the Maximum
PWM Duty Cycle (it is an input to the Duty Cycle
Limiter). With zero oscillator deadtime, the Maximum
PWM Duty Cycle is typically 45%. In many
applications, care should be taken that C
T
not be made so
large as to extend the Maximum Duty Cycle beyond
50%. This can be accomplished by using a stable 470pF
capacitor for C
T
.
PWM SECTION
Pulse Width Modulator
The PWM section of the ML4841 is straightforward, but
there are several points which should be noted. Foremost
among these is its inherent synchronization to the PFC
section of the device, from which it also derives its basic
timing (at the PFC frequency in the ML4841-1, and at
twice the PFC frequency in the ML4841-2). The PWM is
capable of current-mode or voltage mode operation. In
current-mode applications, the PWM ramp (RAMP 2) is
usually derived directly from a current sensing resistor or
current transformer in the primary of the output stage, and
is thereby representative of the current flowing in the
converter’s output stage. DC I
LIMIT
, which provides
cycle-by-cycle current limiting, is typically connected to
RAMP 2 in such applications. For voltage-mode operation
or certain specialized applications, RAMP 2 can be
connected to a separate RC timing network to generate a
voltage ramp against which V
DC
will be compared. Under
these conditions, the use of voltage feedforward from the