參數資料
型號： ML6430
廠商： Fairchild Semiconductor Corporation
英文描述： Genlocking Sync Generator with Digital Audio Clock for NTSC, PAL & VGA(用于NTSC, PAL & VGA數字式音頻同步時鐘發(fā)生器)
中文描述： 同步鎖相同步發(fā)生器用于NTSC，PAL與數字音頻時鐘
文件頁數： 10/33頁
文件大小： 384K
代理商： ML6430
ML6430/ML6431
10
FUNCTIONAL DESCRIPTION
(Continued)
Table 4. NTSC/ PAL Clock Rate Range vs. Crystal Input
DISABLING AUTOMATIC VCR SIGNAL DETECTION
DEVICE
ML6430
ML6431
DISABLE VCR SIGNAL DETECTION
No. Detection function is always on.
Yes. Detection function can be disabled
or enabled via serial bus only. This
feature is enabled by default.
Table 5.
In the ML6430, the VCR detection circuit is always
enabled. This circuit detects the presence of a VCR input
signal at C
VIN
/ H
SYNC
(pin 6) and automatically adjusts
the gain settings for the digital PLL to optimize locking
performance. This circuit scans for head switching greater
than the thresholds selected by the user threshold bits (via
serial bus) and then increases the phase gain of the digital
PLL to compensate.
In the ML6431, the VCR detection circuit operates the
same as the ML6430 with the additional ability to disable
or enable the VCR detection circuit to optimize for low
jitter performance. This feature is enabled by default.
This feature can be disabled in the ML6431 only by
setting the appropriate values in Register 7, Bit 0 via the
serial bus interface (see Table 11). When the VCR detect
circuit is disabled, the ML6431 is optimized for low jitter
performance.
PULSE GENERATOR MODE
54MHz Input or Any 4X Clock
The 54MHz pin (pin 3) is an input that clocks the
horizontal and vertical counters. In this mode, the
ML6430 or ML6431 is used as a pulse generator. The
input signal at can be any 4X clock; for example, 54MHz
(4 x CCIR clock rate of 13.5MHz), 49.09MHz (4 x Square
Pixel clock rate of 12.27MHz), or 57.27 MHz (4 x Fsc
clock rate of 14.31MHz for NTSC color subcarrier). This
input is limited to 70MHz.
As a pulse generator, the sync, clamp, blanking, and
clock signals are derived from the clock input at the
54MHz pin. This mode is activated by setting the
appropriate values in Register 7 via the serial bus. See
Tables 10 or 11.
USING F
RESET
FOR NTSC vs. PAL MODES
In NTSC mode, F
RESET
(pin 22) goes low on the high-to-
low transition of the FIELD ID pin (pin 17) and the
beginning of line 1 (see Figure 2).
In the PAL mode, F
RESET
(pin 22)goes low on the low-to-
high transition of the FIELD ID pin and the end of line
310 (see Figure 3).
CENTER FREQUENCY AND ± RANGE FOR EACH FREQUENCY
STANDARD OF THE ML6431
VIDEO STANDARD
CLOCK RATE
CLOCK RATE
ACCURACY
3.58MHz Crystal
NTSC Square Pixel
NTSC 601
NTSC 4fsc
PAL Square Pixel
PAL 601
PAL 4fsc
4.43MHz Crystal
NTSC Square Pixel
NTSC 601
NTSC 4fsc
PAL Square Pixel
PAL 601
PAL 4fsc
4xClk= 49.09MHz
4xClk= 54.00MHz
4xClk= 57.27MHz
4xClk= 59.00MHz
4xClk= 54.00MHz
4xClk= 35.47MHz
+8.35%/ –5.19%
+6.07%/ –7.18%
+7.15%/ –6.23%
+7.47%/ –5.93%
+6.07%/–7.18%
+7.64%/ –5.77%
4xClk= 49.09MHz
4xClk= 54.00MHz
4xClk= 57.27MHz
4xClk= 59.00MHz
4xClk= 54.00MHz
4xClk= 35.47MHz
+8.28%/ –5.23%
+7.81%/ –5.64%
+6.00%/ –7.18%
+7.27%/ –6.13%
+7.81%/–5.64%
+7.05%/ –6.31%
CENTER FREQUENCY AND ± RANGE FOR EACH FREQUENCY
STANDARD OF THE ML6430
VIDEO STANDARD
CLOCK RATE
CLOCK RATE
ACCURACY
3.58MHz Crystal
NTSC Square Pixel
NTSC 601
NTSC 4fsc
PAL Square Pixel
PAL 601
PAL 4fsc
4.43MHz Crystal
NTSC Square Pixel
NTSC 601
NTSC 4fsc
PAL Square Pixel
PAL 601
PAL 4fsc
4xClk= 49.09MHz
4xClk= 54.00MHz
4xClk= 57.27MHz
4xClk= 59.00MHz
4xClk= 54.00MHz
4xClk= 35.47MHz
+8.35%/ –5.19%
+6.07%/ –7.18%
+7.15%/ –6.23%
+4.01%/ –9.10%
+6.07%/–7.18%
+9.58%/ –4.14%
4xClk= 49.09MHz
4xClk= 54.00MHz
4xClk= 57.27MHz
4xClk= 59.00MHz
4xClk= 54.00MHz
4xClk= 35.47MHz
+8.28%/ –5.23%
+7.81%/ –5.64%
+6.00%/ –7.18%
+7.27%/ –6.13%
+7.81%/–5.64%
+7.05%/ –6.31%
相關PDF資料
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