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參數(shù)資料
| 型號： | ML6430 |
| 廠商： | Fairchild Semiconductor Corporation |
| 英文描述： | Genlocking Sync Generator with Digital Audio Clock for NTSC, PAL & VGA(用于NTSC, PAL & VGA數(shù)字式音頻同步時(shí)鐘發(fā)生器) |
| 中文描述： | 同步鎖相同步發(fā)生器用于NTSC，PAL與數(shù)字音頻時(shí)鐘 |
| 文件頁數(shù)： | 3/33頁 |
| 文件大?。?/td> | 384K |
| 代理商： | ML6430 |
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ML6430/ML6431
3
PIN
NAME
FUNCTION
1
P2/S
DATA
This is a dual function pin. If presets
are enabled, refer to Table 7. If presets
are disabled, serial bus data input.
2
P3/S
CLK
This is a dual function pin. If presets
are enabled, refer to Table 7. If presets
are disabled, serial bus clock input.
3
SLEEP
/54MHz
Hardware sleep mode: when low,
disables entire chip for ultra-low
power dissipation. Sleep mode can
also be enabled/disabled via serial bus
(Register 8). 54MHz is a clock input.
This can be any 4X clock up to
70MHz used for pulse generation.
4
V
CC
S
Analog supply for sync separator.
5
GND S
Analog ground for sync separator.
6
CV
IN
/H
SYNC
Composite video input; video input in
typical composite video applications,
or Y input for YUV applications, or G
input for RGB applications with sync
on green. For typical VGA or other
high performance display applica-
tions, this input may be supplied with
a TTL level H
SYNC
signal and the
vertical sync input supplied with a TTL
level V
SYNC
signal.
7
CV
REF
Reference voltage for internal sync
slicer. The external capacitor is driven
by a charge pump to follow the sync
tip.
8
V
SYNC
Vertical input for non-composite
sources. This input may be supplied
with a TTL level V
SYNC
signal. For
composite inputs this pin is tied high
or low.
9
V
CC
A
Analog supply pin for analog PLL.
10
GND A
Analog ground for analog PLL.
11
XTAL
IN
Crystal may be parallel tuned 3.58
MHz or 4.43MHz, or may be driven
by an external oscillator at these
frequencies, or at 4x these
frequencies.
12
XTAL
OUT
Crystal drive pin. No connect if using
external oscillator or clock.
PIN
NAME
FUNCTION
13
FREERUN
Forces the PLL to run at a selected
standard without syncing to a video
signal. Accuracy is ±20ppm in
FREERUN with ideal crystal, otherwise
locked to video source
14
NOSIGNAL Indicates video signal activity has not
been detected at the composite input.
If NOSIGNAL = low, this condition
does not imply that lock has been
established. The NOSIGNAL pin can
be tied to FREERUN to create a local
loop in which the genlock will not try
to lock until a signal is detected at the
input.
15
LOCKED
Indicates when digital PLL is locked to
incoming video signal.
16
(ML6430) AUDIOCLK
Digital audio clock output.
Programmable for 32kHz, 44.1kHz or
48kHz output.
16
(ML6431) AUDIOCLK/PHERROUT
This is a dual mode pin. Pin is selected
via serial bus (Register 7). AUDIOCLK
is an audio clock signal (see Table 9).
PHERROUT indicates whether
incoming HSYNC is ahead or behind
output HSYNC.
17
FIELD ID
Field Flag: Odd = 1, Even = 0
18
2X CLOCK
2X oversampled PIXEL CLOCK &
Output of Digital PLL. Nominal
frequency of 27MHz
19
1X CLOCK/4X CLOCK
1X pixel clock. Nominal frequency
of 13.5MHz or 54MHz ±20ppm in
FREERUN with ideal crystal, otherwise
locked to video source. PAL 4X CLOCK
not available (no 4x4.4336MHz clock).
20
GND B
Digital ground for output driver
buffers.
21
V
CC
B
Digital supply for output driver buffers.
22
F
RESET
Frame reset; active low for one half
line at the high to low transition of
field ID. In NTSC mode, FRESET goes
low on the high-to-low transition on
the Field ID pin and at the beginning
of line 1 (see Figure 2). In PAL mode,
FRESET goes low on the high-to-low
transition on the Field ID pin and at
the end of line 310 (see Figure 3).
PIN DESCRIPTION
(NOTE: ML6430 and ML6431 pin functions are identical except for pin 16. See below)
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