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參數(shù)資料
| 型號： | ML6510CQ-130 |
| 英文描述： | Series Programmable Adaptive Clock Manager (PACMan⑩) |
| 中文描述： | 系列可編程自適應(yīng)時鐘管理器（吃豆⑩） |
| 文件頁數(shù)： | 13/18頁 |
| 文件大?。?/td> | 603K |
| 代理商： | ML6510CQ-130 |
13
ML6510
TABLE 2: ML6510-130 ROM CODES
SELECTION BITS
INPUT OUTPUT
FREQ
CONFIGURATION CODE
FREQ
(MHz)
CODE DESCRIPTION
0
PECL Input Clock, 1x mode
1
PECL Input Clock, 0.5x mode
2
PECL Input Clock, 2x mode
3
PECL Input Clock, 1x mode
4
TTL Input Clock, 1x mode
5
TTL Input Clock, 0.5x mode
6
TTL Input Clock, 2x mode
7
TEST mode, TTL Input clock
ROMMSB
0
0
0
0
1
1
1
1
MCLK
0
0
1
1
0
0
1
1
MD
OUT
(MHz)
0
1
0
1
0
1
0
1
CS
1
1
1
1
0
0
0
0
CM
1
1
1
0
0
0
0
—
R1, R0
00
01
00
00
00
01
00
—
M
0
5
2
0
0
5
2
—
N
0
2
5
0
0
2
5
—
DDSK
0
0
0
0
0
0
0
—
TEST
0
0
0
0
0
0
0
1
80-130 80-130
80-160
40-65
80-130 80-130
80-130 80-130
80-130
40-65
0-50
40-80
80-130
40-65
80-130
0-50
TABLE 1: ML6510-80 ROM CODES
SELECTION BITS
INPUT
FREQ
(MHz)
40-80
40-80
20-40
40-80
40-80
40-80
20-40
0-50
OUTPUT
FREQ
(MHz)
40-80
20-40
40-80
40-80
40-80
20-40
40-80
0-50
CONFIGURATION CODE
CODE DESCRIPTION
0
PECL Input Clock, 1x mode
1
PECL Input Clock, 0.5x mode
2
PECL Input Clock, 2x mode
3
PECL Input Clock, 1x mode
4
TTL Input Clock, 1x mode
5
TTL Input Clock, 0.5x mode
6
TTL Input Clock, 2x mode
7
TEST mode, TTL Input clock
ROMMSB
0
0
0
0
1
1
1
1
MCLK
0
0
1
1
0
0
1
1
MD
OUT
0
1
0
1
0
1
0
1
CS
1
1
1
1
0
0
0
0
CM R1, R0
1
1
1
0
0
0
0
—
M
0
5
2
0
0
5
2
—
N
0
2
5
0
0
2
5
—
TEST
0
0
0
0
0
0
0
1
01
10
01
01
01
10
01
—
Figure 6. AUX Mode Waveform.
MCLK
(Input to ML6510)
MD
OUT
(Input to ML6510)
tA1
tA2
tA5
18
02
01
M5
N0
tA3
tA4
M4
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相關(guān)代理商/技術(shù)參數(shù) |
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|---|---|
| ML6510CQ80 | 制造商:Rochester Electronics LLC 功能描述:- Bulk |
| ML6510CQ-80 | 制造商:MICRO-LINEAR 制造商全稱:MICRO-LINEAR 功能描述:Series Programmable Adaptive Clock Manager (PACMan⑩) |
| ML6516244 | 制造商:MICRO-LINEAR 制造商全稱:MICRO-LINEAR 功能描述:16-Bit Buffer/Line Driver with 3-State Outputs |
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| ML6516244CT | 制造商:MICRO-LINEAR 制造商全稱:MICRO-LINEAR 功能描述:16-Bit Buffer/Line Driver with 3-State Outputs |
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