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ML66525 Family User’s Manual
Chapter 2
CPU Architecture
2 - 26
Each segment is assigned an internal segment offset address of 0 to 0FFFFH.
The address
calculation to determine the addressed target is performed with a 16-bit offset address and any
resulting overflow or underflow is ignored, so TSR does not change.
The TSR value at reset
is 00H.
(3)
Data segment register (DSR)
7
6
54
32
10
DSR
00
“0”
At reset
“0” indicates that a value of “0” must be written.
If read, a value of “0” will be obtained.
Address: 0009 [H]
R/W access: R/W
DSR specifies the segment in data memory space to which the data currently in use belongs.
DSR is an 8-bit register and is assigned to the SFR area.
The contents of DSR can be
overwritten by instructions that use SFR addressing.
Only bits 0 to 3 of DSR are valid.
If
read, a value of “0” will be obtained for bits 4 to 7.
If writing to DSR, “0” must be written to
bits 4 to 7.
2.4
Addressing Modes
The ML66525 family has two independent memory spaces, the data memory space and the
program memory space.
Addressing can be roughly classified into two modes, corresponding
to each memory space.
The data memory space is referred to as “RAM space”, since it normally consists of random
access memory (RAM).
The addressing for this space is referred to as “RAM addressing”.
The program memory space is referred to as “ROM space”, since it normally consists of
read-only memory (ROM). The addressing for this space is referred to as “ROM addressing”.
ROM addressing is classified as immediate addressing contained in instruction codes, table
data addressing for data (normally read-only data) in a ROM space table, and program code
addressing for programs in the ROM space.
ROM window addressing is a unique method of addressing.
It involves accessing table data
in the ROM space using the above RAM addressing methods.
Data in a table segment is read
through a data segment window specified and opened by the program.
2.4.1 RAM Addressing
This addressing mode specifies addresses for program variables in the RAM space.
Available addressing formats include: register addressing, page addressing, direct data
addressing, pointing register indirect addressing and special bit area addressing.