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參數(shù)資料
| 型號： | ML67Q5002LA |
| 廠商： | LAPIS SEMICONDUCTOR CO LTD |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | 32-BIT, FLASH, 60 MHz, RISC MICROCONTROLLER, PBGA144 |
| 封裝： | 11 X 11 MM, 0.80 MM PITCH, PLASTIC, LFBGA-144 |
| 文件頁數(shù)： | 23/25頁 |
| 文件大?。?/td> | 233K |
| 代理商： | ML67Q5002LA |
FEDL675001-01
OKI Semiconductor
ML675001/67Q5002/67Q5003
6/24
LIST OF PINS
Pin
Primary Function
Secondary Function
LQFP
BGA
Symbol
I/O
Description
Symbol
I/O
Description
1
A1
TEST1
—
Test mode input
—
2
B1
PIOB[7]
I/O
General port (with interrupt function)
SRXD
I
SIO receive signal
3
C3
FWR
I
Test mode inout
—
4
C1
RESET_N
I
Reset input
—
5
D3
VDD_IO
VDD
IO power supply
—
6
C2
XD[0]
I/O
External data bus
—
7
D1
XD[1]
I/O
External data bus
—
8
E3
XD[2]
I/O
External data bus
—
9
D2
XD[3]
I/O
External data bus
—
10
E1
XD[4]
I/O
External data bus
—
11
E4
GND
—
12
E2
CLKMD0
I
Clock mode input
—
13
F1
XD[5]
I/O
External data bus
—
14
F2
XD[6]
I/O
External data bus
—
15
F4
GND
—
16
F3
XD[7]
I/O
External data bus
—
17
G2
CLKMD1
I
Clock mode input
—
18
G4
VDD_IO
VDD
I/O power supply
—
19
G3
XD[8]
I/O
External data bus
—
20
G1
XD[9]
I/O
External data bus
—
21
H3
XD[10]
I/O
External data bus
—
22
H4
VDD_CORE
VDD
CORE power supply
—
23
H2
NC
—
NC
—
24
J2
XD[11]
I/O
External data bus
—
25
H1
XD[12]
I/O
External data bus
—
26
J4
VDD_IO
VDD
I/O power supply
—
27
K2
XD[13]
I/O
External data bus
—
28
J1
XD[14]
I/O
External data bus
—
29
J3
XD[15]
I/O
External data bus
—
30
K3
XA[0]
O
External address output
—
31
K1
XA[1]
O
External address output
—
32
L2
XA[2]
O
External address output
—
33
K4
XA[3]
O
External address output
—
34
L1
GND
—
35
M2
XA[4]
O
External address output
—
36
M1
XA[5]
O
External address output
—
37
N1
XA[6]
O
External address output
—
38
N2
XA[7]
O
External address output
—
39
L3
XA[8]
O
External address output
—
40
N3
XA[9]
O
External address output
—
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