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參數(shù)資料
| 型號： | ML7019 |
| 廠商： | OKI SEMICONDUCTOR CO., LTD. |
| 元件分類： | Codec |
| 英文描述： | Single Rail Dual Channel Codec(雙通道編碼譯碼器) |
| 中文描述： | 單軌雙通道編解碼器（雙通道編碼譯碼器） |
| 文件頁數(shù)： | 10/18頁 |
| 文件大?。?/td> | 126K |
| 代理商： | ML7019 |
9
l
ML7019
Preliminary
v
RECOMMENDED OPERATING CONDITIONS
Parameter
Symbol
Conditions
Min.
Typ.
Max.
Unit
Power Supply Voltage
V
DD
V
AIN
V
IH
V
IL
Voltage must be fixed
4.75
5.0
5.25
V
Analog Input Voltage
Gain = 1
-
-
3.4
V
PP
V
Digital Input High Voltage
2.2
-
V
DD
0.8
Digital Input Low Voltage
XSYNC, RSYNC,
BCLK, DIN, PDN
0
-
V
256
384
512
Clock Frequency
F
CLK
BCLK
768
1024
1536
KHz
1544
-
2048
8
4096
-
Sync Pulse Frequency
F
SYNC
D
CLK
T
IR
T
IF
T
X S
T
SX
T
RS
T
SR
T
WS
T
DS
T
DH
R
DL
XSYNC, RSYNC
KHz
Clock Duty Ratio
BCLK
40
50
60
%
Digital Input Rise Time
XSYNC, RSYNC,
-
-
50
ns
Digital Input Fall Time
BCLK, DIN, PDN
-
-
50
ns
Transmit Sync Pulse
BCLK to XSYNC
50
-
-
ns
Setting Time
XSYNC to BCLK
-
-
ns
Receive Sync Pulse
BCLK to RSYNC
50
-
-
ns
Setting Time
RSYNC to BCLK
50
-
-
ns
Sync Pulse Width
XSYNC, RSYNC
1 BCLK
-
100
μ
s
DIN set-up Time
DIN
50
-
-
ns
DIN Hold Time
DIN
50
-
-
ns
Pull-up register, DOUT
0.5
-
-
K
Digital Output Load
DOUT
-
-
50
pF
C
DL
C1A, C2A, C3A,
C1B, C2B, C3B
Transmit gain stage,
Gain = 1
-
-
50
pF
V
DD
/ 2
-100
-
V
DD
/ 2
+100
mV
Analog Input Allowable
DC offset
V
OFF
Transmit gain stage,
Gain = 10
V
DD
/ 2
-10
-
V
DD
/ 2
+10
500
mV
Allowable J itter Width
XSYNC, RSYNC
-
-
ns
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