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參數(shù)資料
| 型號： | ML7019 |
| 廠商： | OKI SEMICONDUCTOR CO., LTD. |
| 元件分類： | Codec |
| 英文描述： | Single Rail Dual Channel Codec(雙通道編碼譯碼器) |
| 中文描述： | 單軌雙通道編解碼器（雙通道編碼譯碼器） |
| 文件頁數(shù)： | 7/18頁 |
| 文件大?。?/td> | 126K |
| 代理商： | ML7019 |
6
l
ML7019
Preliminary
DOUT
DOUT is a data output pin.
Signal which consist of a total 28 bits configured by the voice band PCM signal(16
bits for 2CH), the echo bit(6 bits for latch signal and 2 bits for power down state
indication), and empty bit(4 bits),
The output signal is output from CH1's MSD bit in a sequential order, synchronizing
with the rising edge of the BCLK signal.
The first bit of DOUT may be output at the rising edge of the XSYNC signal, based
on the timing between BCLK and XSYNC.
This pin is in a high impedance state during power saving state or power down
state.
A pull-up resistor must be connected to this pin because it is an open drain output.
This device is compatible with ITU-T recommendation on coding law and output
coding format.
PCMIN / PCMOUT
INPUT / OUTPUT
Level
ALOW = 0 (
μ
-law )
MSD
1 0 0 0 0 0 0 0
1 1 1 1 1 1 1 1
0 1 1 1 1 1 1 1
0 0 0 0 0 0 0 0
ALOW = 1 ( A-law )
MSD
1 0 1 0 1 0 1 0
1 1 0 1 0 1 0 1
0 1 0 1 0 1 0 1
0 0 1 0 1 0 1 0
+ Full scale
+ 0
- 0
- Full scale
PDN
Power down control signal.
When PDN is at logic "0" level, both CH1 and CH2 circuits are in a power down
state. Also the all internal latches are in initial state(logic "0" level).
ALAW
Control signal input of the companding law selection.
The CODEC will operate in the
μ
-law when this pin is at a logic "0" level and the
CODEC will operate in the A-law when this pin is at a logic "1" level. The CODEC
operates in the
μ
-law if the pin is left open, as this pin is internally pulled down.
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