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參數(shù)資料
| 型號(hào)： | ML7019 |
| 廠商： | OKI SEMICONDUCTOR CO., LTD. |
| 元件分類： | Codec |
| 英文描述： | Single Rail Dual Channel Codec(雙通道編碼譯碼器) |
| 中文描述： | 單軌雙通道編解碼器（雙通道編碼譯碼器） |
| 文件頁數(shù)： | 5/18頁 |
| 文件大?。?/td> | 126K |
| 代理商： | ML7019 |
4
l
ML7019
Preliminary
VDD
Power supply for +5V.
A power supply for an analog circuit of the system which the device is applied
should be used a bypass capacitor of 0.1
μ
F with excellent high frequency
characteristics and a capacitor of 10
μ
F to 20
μ
F should be connected between this
pin and the AG pin if needed.
AG
Analog signal ground.
DG
Ground for the digital signal circuits.
This ground is separate from the analog signal ground. The DG pin must be
connected to the AG pin on the printed circuit board to make a common analog
ground.
SGC
Used to generate the signal ground voltage level by connecting a bypass capacitor.
Connect a 0.1
μ
F capacitor with excellent high frequency characteristics between
the AG pin and the SGC pin.
BCLK
Shift clock signal input for the DIN signals.
The frequency, equal to the data rate, is 256, 384, 512, 768, 1024, 1536, 1544,
2048, 4096KHz.Setting this signal to logic "1" or "0" drives both transmit and
receive circuits to the power saving state.
RSYNC
Receive synchronizing signal input.
Signals in the receive section are synchronized by this synchronizing signal. This
signal must be synchronized in phase with the BCLK (generated from the same
clock source as BCLK). The frequency should be 8KHz
±
50ppm to guarantee the
AC characteristics which are mainly the frequency characteristic of the receive
section.
However, if the frequency characteristic of the system used is not strictly specified,
this device can operate in the range of 6KHz to 9KHz, but the electrical
characteristics in this specifications are not guaranteed.
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