參數(shù)資料
型號: ML9040-Axx
廠商: OKI SEMICONDUCTOR CO., LTD.
英文描述: DOT MATRIX LCD CONTROLLER WITH 16-DOT COMMON DRIVER AND 40-DOT SEGMENT DRIVER
中文描述: 點陣LCD控制器的16交通部通用驅動器和40段驅動交通部
文件頁數(shù): 14/47頁
文件大小: 434K
代理商: ML9040-AXX
Semiconductor
ML9040-Axx/-Bxx
14
Timing Generator Circuit
This circuit is used to generate timing signals to activate internal operations upon receipt
of CPU instruction and also from such internal circuits as the DD RAM, CG RAM, and CG
ROM.
It is designed so that the internal operation caused by accessing from the CPU will not
interfer e with the internal operation caused by LCD driving. Consequently, when data
is written from the CPU to DD RAM, flickering does not occur in a display area other than
the display area where the data is written.
In addition, this circuit generates the transfer signal to MSM5259 for display character
expansion.
Display Data RAM (DD RAM)
This RAM is used to store display data of 8-bit character codes (see Table 2).
DD RAM address corresponds to the display position of the LCD. The correspondence
between the two is described in the following.
DD RAM address (set to ADC) is expressed in hexadecimal notation as shown below:
(1)Corresponden ce between address and display position in the 1-line display mode
First
digit
01
02
03
04
(2)When the ML9040-Axx/-Bxx alone is used, up to 8 characters can be displayed from the
first to eighth digit.
First
digit
01
02
03
04
05
06
07
When the display is shifted by instruction, the correspondence between the LCD
display position and the DD RAM address changes as shown below:
00
2
3
4
5
4E
79
4F
80
MSB
LSB
Display position
DD RAM address (hex.)
00
2
3
4
5
6
7
8
4F
First
digit
00
2
01
3
02
4
03
5
04
6
05
7
06
8
(Display
shifted
to right)
First
digit
01
02
2
03
3
04
4
05
5
06
6
07
7
08
8
(Display
shifted
to left)
LSB
MSB
Hexadecimal notation
Hexadecimal notation
DB
0
DB
6
ADC
L
L
2
A
(Example)
When DD RAM
address is 2A
H
L
H
L
H
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