參數(shù)資料
型號: ML9040-Axx
廠商: OKI SEMICONDUCTOR CO., LTD.
英文描述: DOT MATRIX LCD CONTROLLER WITH 16-DOT COMMON DRIVER AND 40-DOT SEGMENT DRIVER
中文描述: 點陣LCD控制器的16交通部通用驅(qū)動器和40段驅(qū)動交通部
文件頁數(shù): 32/47頁
文件大?。?/td> 434K
代理商: ML9040-AXX
Semiconductor
ML9040-Axx/-Bxx
32
H
R/W
Instruction code
L
RS
BF
DB
7
O
6
DB
6
O
5
DB
5
O
4
DB
4
O
3
DB
3
O
2
DB
2
O
1
DB
1
O
0
DB
0
H
R/W
Instruction code
H
RS
P
7
DB
7
P
6
DB
6
P
5
DB
5
P
4
DB
4
P
3
DB
3
P
2
DB
2
P
1
DB
1
P
0
DB
0
(10) Busy flag and address counter read (Execution time is 1
m
s.)
The busy flag (BF) is output by this instruction to indicate whether the MSM6222B-xx
is engaged in internal operations (BF = "H") or not (BF = "L").
When BF = "H", no new instruction is accepted. It is therefore necessary to verify BF =
"L" before inputting a new instruction.
When BF = "L", a correct address counter value is output. The address counter value
must match the DD RAM address or CG RAM address. The decision of whether it is
a DD RAM address or CG RAM address is made by the address previously set.
Since the address counter value when BF = "H" is sometimes incremented or decremented
by 1 during internal operations, it is not always a correct value.
(11) DD RAM and CG RAM data read
Character codes (bits P
7
to P
0
) are read from the DD RAM, while character patterns (P
7
to P
0
) from the CG RAM.
Selection of DD RAM or CG RAM is decided by the address previously set.
After reading those data, the address counter (ADC) is incremented or decremented by
1 as set by the shift mode mentioned in item "(3) shift mode set".
The execution time, when the OSC oscillation frequency is 250 kHz, is 40
m
s.
(Note) Conditions for the reading of correct data:
1
When the DD RAM address set or CG RAM address set is input before
inputting this instruction.
2
When the cursor/display shift is input before inputting this instruction in
case the character code is read.
3
Data after the second reading from RAM when read more than 2 times.
Correct data is not output in any other case.
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