
MMC2001
REFERENCE MANUAL
INTEGER CPU
MOTOROLA
2-11
2.8.4 Bus Operation
The following sections provide a functional description of the system bus, the signals
that control it, and the bus cycles provided for data transfer operations. They also
describe the error conditions and reset operation.
Table 2-2 MCORE Bus Signals
Signal Name
Address and Transfer Attributes
ADDR[31:0]
Address Bus
Pins
Active
I/O
Description
32
High
O
Driven by the MCORE to specify the physical address of
the bus transaction.
Driven by the MCORE along with the address. Driven
high indicates that a read access is in progress. Driven
low indicates that a write access is in progress.
Driven by the MCORE along with the address. Specifies
the data transfer size for the transaction.
Driven by the MCORE along with the address. Indicates
the type of access for the current bus cycle.
R/W
Read/Write
1
High
O
TSIZ[1:0]
Transfer Size
TC[2:0]
Transfer Code
Transfer Request/Transfer Busy
2
High
O
3
High
O
TREQ
Transfer Request
1
Low
O
Driven by the MCORE along with the address and trans-
fer attributes to indicate that a new access has been
requested.
Driven by the MCORE to indicate that an access is in
progress. This signal is driven for the duration of a cycle
and may be held asserted for multiple transfers.
TBUSY
Transfer Busy
1
Low
O
Data
DATA[31:0]
Data Bus
32
High
O
Driven by the MCORE when it “owns” the bus and it initi-
ated a write transaction to a slave device. Eight (byte), 16
(halfword), or 32 (word) bits of data can be transferred
per access.
Driven by the slave in a read transaction. Eight (byte), 16
(halfword), or 32 (word) bits of data can be transferred
per access.
I
Transfer Cycle Termination and Status
TA
Transfer Acknowledge
1
Low
I
Driven by the slave device to which the current transac-
tion was addressed. Indicates that the slave has received
the data on the write cycle or returned data on the read
cycle.
Driven by the slave device to which the current transac-
tion was addressed. Indicates that an error condition has
occurred during the bus cycle.
Driven by the MCORE to indicate that the transfer is to
be aborted immediately.
TEA
Transfer Error
Acknowledge
ABORT
Abort
Power Management
1
Low
I
1
Low
O
LPMD[1:0]
Low-Power Modes
2
Low
O
Driven by the MCORE to indicate whether the core is
running in normal mode or has just executed a low power
mode instruction.
Debug
DBGACK
Debug Mode
1
Low
O
Driven by the MCORE to indicate that debug mode has
been entered.