
Page
Section
Definiti-
on
Details of Changes
PreviousEdition (Ver.1.0)
New Edition (Ver.2.2)
VII-22
Cautions
Addition
When data is written to the 16-bit timer preset register,
even the MOVW instruction of 16-bit access is counted as
a 8-bit unit data. For this reason, if data is loaded from
preset register into compare register while the data is
written, correct value may not be loaded.
VII-41
Line 1
Change
The standard IGBT output starts count up with the
external interrupt input signal as a trigger.
A trigger factor of the standard IGBT output activation can
be selected from external interrupt pins 0 to 3.
Line
3to8
Addition
-
Destription on IGBT trigger selection
VII-47
Line 1
Change
The high precision IGBT output starts count up with
the external interrupt input signal as a trigger.
An activation trigger of the high precision IGBT output can
be selected from external interrupt 0 to 3.
Line
3to8
Addition
-
Destription on IGBT trigger selection
VII-58
-
Addition
-
Setup example (14)
*Set P14, P15 as special function pins after setup (11) to
(13).
VII-63
Table
7-13-1
Addition
-
* At cascade connection, timer 8 interrupt factor is only
counter-clear.
VII-65
Setup
example
(6)
Change
(6)Set the interrupt generation cycle
TM7PR1(x'3F75', x'3F74')=x'FFFF'
TM8PR1(x'3F85', x'3F84')=x'86A0'
(6)Set the interrupt generation cycle
TM7PR1(x'3F75', x'3F74')=x'869F'
TM8PR1(x'3F85', x'3F84')=x'0001'
X-10
Figure
10-2-1
Change
Note : After reset is released, the oscillation
stabilization wait period is fixed at fs/214.
Note : After reset is released, the oscillation stabilization
wait period is fixed at fs/210.
XI-2
Table
11-1-1
Addition
-
* Unselectable when parity bit is not added.
XI-2
Figure
11-2-5
Addition
-
* Do not set when parity bit is not added.
XI-36
Addition
-
Description of transfer bit count of 7 bits data and the first
transfer bit in UART communication is added
XI-37
Deletion
Following reference page guide is deleted
Transfer Bit Count and First Transfer Bit
Refer to: XI-14
Reception Bit Count and First Transfer Bit
Refer to: XI-14
-
XI-41
Table
11-3-8-
1,2
Change
-
Organization of the table is updated.
XII-3
Figure
12-1-1
Change
XIV-2
|
XIV-5
Change
-
Organization of the section is updated.
MN101C54 LSI User's Manual Record of Changes (Ver. 1.0 to Ver. 2.2) (2/3)
SBO2/P03
SBI2/P04
M
U
X
SC2IOM
SC2SBIS
SWAP MSB
LSB
Read/Write
Start condition
detection circuit
SC2TRB
Shift register
SBO2/P03
SBI2/P04
M
U
X
SC2IOM
SC2SBIS
SWAP MSB
LSB
Read/Write
Start condition
detection circuit
SC2TRB
Shift register