參數(shù)資料
型號(hào)： MPC107
廠商： Motorola, Inc.
英文描述： 32-Bit Microprocessor(32位微處理器)
中文描述： 32位微處理器（32位微處理器）
文件頁(yè)數(shù)： 39/46頁(yè)
文件大小： 585K
代理商： MPC107
MPC107 Hardware Specifications (Rev 0.2)
PRELIMINARYSUBJECT TO CHANGE WITHOUT NOTICE
39
System Design Information
1.7 System Design Information
This section provides electrical and thermal design recommendations for successful application of the
MPC107.
1.7.1 PLL Power Supply Filtering
The AVdd and LAVdd power signals are provided on the MPC107 to provide power to the peripheral logic/
memory bus PLL, the 603e processor PLL, and the SDRAM clock delay-locked loop (DLL), respectively.
To ensure stability of the internal clocks, the power supplied to the AVdd and LAVdd input signals should
be Tltered of any noise in the 500kHz to 10MHz resonant frequency range of the PLLs. A separate circuit
similar to the one shown in Figure 23 using surface mount capacitors with minimum effective series
inductance (ESL) is recommended for each of the AVdd and LAVdd power signal pins. Consistent with the
recommendations of Dr. Howard Johnson in
High Speed Digital Design: A Handbook of Black Magic
(Prentice Hall, 1993), multiple small capacitors of equal value are recommended over using multiple values.
The circuits should be placed as close as possible to the respective input signal pins to minimize noise
coupled from nearby circuits. Routing directly as possible from the capacitors to the input signal pins with
minimal inductance of vias is important but proportionately less critical for the LAVdd pin.
Figure 23. PLL Power Supply Filter Circuit
1.7.2 Power Supply Voltage Sequencing
The notes in Table 2 contain cautions illustrated in Figure 2 about the sequencing of the external bus
voltages and internal voltages of the MPC107. These cautions are necessary for the long term reliability of
the part. If they are violated, the electrostatic discharge (ESD) protection diodes will be forward biased and
excessive current can ow through these diodes. Figure 2 shows a typical ramping voltage sequence where
the DC power sources (voltage regulators and/or power supplies) are connected as shown in Figure 24. The
voltage regulator delay shown in Figure 2 can be zero if the various DC voltage levels are all applied to the
target board at the same time. The ramping voltage sequence shows a scenario in which the Vdd/AVdd/
LAVdd power plane is not loaded as much as the OVdd/GVdd power plane and thus Vdd/AVdd/LAVdd
ramps at a faster rate than OVdd/GVdd.
If the system power supply design does not control the voltage sequencing, the circuit of Figure 24 can be
added to meet these requirements. The MUR420 diodes of Figure 24 control the maximum potential
difference between the 3.3V bus and internal voltages on power-up and the 1N5820 Schottky diodes
regulate the maximum potential difference on power-down.
Vdd
AVdd or LAVdd
10
W
2.2 μF
2.2 μF
GND
Low ESL surface mount capacitors
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