參數(shù)資料
型號(hào): MPC107
廠商: Motorola, Inc.
英文描述: 32-Bit Microprocessor(32位微處理器)
中文描述: 32位微處理器(32位微處理器)
文件頁數(shù): 4/46頁
文件大小: 585K
代理商: MPC107
4
MPC107 Hardware Specifications (Rev 0.2)
PRELIMINARYSUBJECT TO CHANGE WITHOUT NOTICE
Features
1.2 Features
The MPC107 provides an integrated high-bandwidth, high-performance interface between up to two 60x
processors, the PCI bus, and main memory. This section summarizes the features of the MPC107. Major
features of the MPC107 are as follows:
Memory interface
64-/32-bit 100-MHz bus
Programmable timing supporting either FPM DRAM, EDO DRAM or SDRAM
High-bandwidth bus (32-/64-bit data bus) to DRAM
Supports one to eight banks of 4-, 16-, 64-, or 128-Mbit memory devices, and up to four banks
of 256-Mbit SDRAM devices
Supports 1-Mbyte to 1-Gbyte DRAM memory
144 Mbytes of ROM space
8-, 32-, or 64-bit ROM
Write buffering for PCI and processor accesses
Supports normal parity, read-modify-write (RMW), or ECC
Data-path buffering between memory interface and processor
Low-voltage TTL logic (LVTTL) interfaces
Port X: 8-, 32-, or 64-bit general-purpose I/O port using ROM controller interface with
programmable address strobe timing
32-bit PCI interface operating up to 66 MHz
PCI 2.1-compliant
PCI 5.0-V tolerance
Support for PCI locked accesses to memory
Support for accesses to PCI memory, I/O, and conTguration spaces
Selectable big- or little-endian operation
Store gathering of processor-to-PCI write and PCI-to-memory write accesses
Memory prefetching of PCI read accesses
Selectable hardware-enforced coherency
PCI bus arbitration unit (Tve request/grant pairs)
PCI agent mode capability
Address translation unit
Some internal conTguration registers accessible from PCI
Two-channel integrated DMA controller (writes to ROM/Port X not supported)
Supports direct mode or chaining mode (automatic linking of DMA transfers)
Supports scatter gatheringread or write discontinuous memory
Interrupt on completed segment, chain, and error
Local-to-local memory
PCI-to-PCI memory
PCI-to-local memory
PCI memory-to-local memory
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