參數(shù)資料
型號(hào)： MPC5125YVN400
廠商： FREESCALE SEMICONDUCTOR INC
元件分類： 微控制器/微處理器
英文描述： 32-BIT, FLASH, 400 MHz, MICROCONTROLLER, PBGA324
封裝： 23 X 23 MM, 2.25 MM HEIGHT, 1 MM PITCH, ROHS COMPLIANT, PLASTIC, MS-034AJJ-1, TEPBGA-324
文件頁數(shù)： 61/92頁
文件大?。?/td> 640K
代理商： MPC5125YVN400
MPC5125 Microcontroller Data Sheet, Rev. 3
Electrical and Thermal Characteristics
Freescale Semiconductor
64
Figure 27. Ethernet Timing Diagram — MII and RMII Rx Signal
Table 28. RMII Rx Signal Timing
Sym
Description
Min
Max
Unit
SpecID
t5
RXD[1:0], RX_DV, RX_ER to TX_CLK setup
4
—
ns
A11.5
t6
TX_CLK to RXD[1:0], RX_DV, RX_ER hold
2
—
ns
A11.6
t7
TX_CLK pulse width high
35%
65%
TX_CLK period1
NOTES:
1 TX_CLK frequency shall be 50 MHz regardless of the data rate. See the RMII specification.
A11.7
t8
TX_CLK pulse width low
35%
65%
TX_CLK period1
A11.8
Table 29. MII Tx Signal Timing
Sym
Description
Min
Max
Unit
SpecID
t9
TX_CLK rising edge to TXD[3:0], TX_EN, TX_ER invalid
3
—
ns
A11.9
t10
TX_CLK rising edge to TXD[3:0], TX_EN, TX_ER valid
—
25
ns
A11.10
t11
TX_CLK pulse width high
35%
65%
TX_CLK Period1
NOTES:
1 The TX_CLK frequency shall be 25% of the nominal transmit frequency, for example, a PHY operating at 100 Mb/s must
provide a TX_CLK frequency of 25 MHz and a PHY operating at 10 Mb/s must provide a TX_CLK frequency of 2.5 MHz. See
the IEEE 802.3 specification.
A11.11
t12
TX_CLK pulse width low
35%
65%
TX_CLK Period1
A11.12
Table 30. RMII Tx Signal Timing
Sym
Description
Min
Max
Unit
SpecID
t13
TX_CLK rising edge to TXD[1:0], TX_EN, TX_ER invalid
3
—
ns
A11.13
t14
TX_CLK rising edge to TXD[1:0], TX_EN, TX_ER valid
—
14
ns
A11.14
t15
TX_CLK pulse width high
35%
65%
TX_CLK Period1
NOTES:
1 TX_CLK frequency shall be 50 MHz regardless of the data rate. See the RMII specification.
A11.15
t16
TX_CLK pulse width low
35%
65%
TX_CLK Period1
A11.16
t4, t8
t3, t7
t1. t5
t2. t6
REF_CLK (Input)
RXD[3:0] (inputs)
RX_DV
RX_ER
REF_CLK is TX_CLK in RMII mode, and is RX_CLK in non-RMII mode
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