參數(shù)資料
型號(hào)： MPC5553MZQ132
廠商： Freescale Semiconductor
文件頁(yè)數(shù)： 12/68頁(yè)
文件大?。?/td> 0K
描述： IC MCU MPC5553 REV A 324-PBGA
產(chǎn)品培訓(xùn)模塊： MPC55xx PitchPak Family
標(biāo)準(zhǔn)包裝： 60
系列： MPC55xx Qorivva
核心處理器： e200z6
芯體尺寸： 32-位
速度： 132MHz
連通性： CAN，EBI/EMI，以太網(wǎng)，SCI，SPI
外圍設(shè)備： DMA，POR，PWM，WDT
輸入/輸出數(shù)： 220
程序存儲(chǔ)器容量： 1.5MB（1.5M x 8）
程序存儲(chǔ)器類(lèi)型： 閃存
RAM 容量： 64K x 8
電壓 - 電源 (Vcc/Vdd)： 1.35 V ~ 1.65 V
數(shù)據(jù)轉(zhuǎn)換器： A/D 40x12b
振蕩器型： 外部
工作溫度： -40°C ~ 125°C
封裝/外殼： 324-BBGA
包裝： 托盤(pán)
配用： MPC5553EVBISYS-ND - KIT EVAL ISYSTEMS MPC5553
MPC5553EVBGHS-ND - KIT EVAL GREEN HILLS SOFTWARE
MPC5553EVB-ND - KIT EVAL MPC5553MZP132
MPC5553EVBE-ND - BOARD EVAL FOR MPC5553
MPC5553 Microcontroller Data Sheet, Rev. 4
Overview
Freescale Semiconductor
2
The MPC5500 family of parts contains many new features coupled with high performance CMOS
technology to provide significant performance improvement over the MPC565.
The MPC5553 has two levels of memory hierarchy. The fastest accesses are to the 8-kilobytes (KB)
unified cache. The next level in the hierarchy contains the 64-KB on-chip internal SRAM and
1.5-megabytes (MB) internal flash memory. The internal SRAM and flash memory hold instructions and
data. The external bus interface is designed to support most of the standard memories used with the
MPC5xx family.
The complex input/output timer functions of the MPC5553 are performed by an enhanced time processor
unit (eTPU) engine. The eTPU engine controls 32 hardware channels. The eTPU has been enhanced over
the TPU by providing: 24-bit timers, double-action hardware channels, variable number of parameters per
channel, angle clock hardware, and additional control and arithmetic instructions. The eTPU is
programmed using a high-level programming language.
The less complex timer functions of the MPC5553 are performed by the enhanced modular input/output
system (eMIOS). The eMIOS’ 24 hardware channels are capable of single-action, double-action,
pulse-width modulation (PWM), and modulus-counter operations. Motor control capabilities include
edge-aligned and center-aligned PWM.
Off-chip communication is performed by a suite of serial protocols including controller area networks
(FlexCANs), enhanced deserial/serial peripheral interfaces (DSPIs), and enhanced serial communications
interfaces (eSCIs).
The MCU has an on-chip enhanced queued dual analog-to-digital converter (eQADC). The 324 and 416
packages have 40-channels.
The system integration unit (SIU) performs several chip-wide configuration functions. Pad configuration
and general-purpose input and output (GPIO) are controlled from the SIU. External interrupts and reset
control are also determined by the SIU. The internal multiplexer submodule (SIU_DISR)provides
multiplexing of eQADC trigger sources and external interrupt signal multiplexing.
The Fast Ethernet (FEC) module is a RISC-based controller that supports both 10 and 100 Mbps
Ethernet/IEEE 802.3 networks and is compatible with three different standard MAC (media access
controller) PHY (physical) interfaces to connect to an external Ethernet bus. The FEC supports the 10 or
100 Mbps MII (media independent interface), and the 10 Mbps-only with a seven-wire interface, which
uses a subset of the MII signals. The upper 16-bits of the 32-bit external bus interface (EBI) are used to
connect to an external Ethernet device. The FEC contains built-in transmit and receive message FIFOs and
DMA support.
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