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| 型號： | MPC5554MZP80 |
| 廠商： | Freescale Semiconductor |
| 文件頁數(shù)： | 2/58頁 |
| 文件大小： | 0K |
| 描述： | IC MCU 32BIT 2MB FLASH 416PBGA |
| 標(biāo)準(zhǔn)包裝： | 40 |
| 系列： | MPC55xx Qorivva |
| 核心處理器： | e200z6 |
| 芯體尺寸： | 32-位 |
| 速度： | 82MHz |
| 連通性： | CAN，EBI/EMI，SCI，SPI |
| 外圍設(shè)備： | DMA，POR，PWM，WDT |
| 輸入/輸出數(shù)： | 256 |
| 程序存儲器容量： | 2MB（2M x 8） |
| 程序存儲器類型： | 閃存 |
| RAM 容量： | 64K x 8 |
| 電壓 - 電源 (Vcc/Vdd)： | 1.35 V ~ 1.65 V |
| 數(shù)據(jù)轉(zhuǎn)換器： | A/D 40x12b |
| 振蕩器型： | 外部 |
| 工作溫度： | -40°C ~ 125°C |
| 封裝/外殼： | 416-BBGA |
| 包裝： | 托盤 |
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MPC5554 Microcontroller Data Sheet, Rev. 4
Electrical Characteristics
Freescale Semiconductor
10
3.7
Power-Up/Down Sequencing
Power sequencing between the 1.5 V power supply and VDDSYN or the RESET power supplies is required
if using an external 1.5 V power supply with VRC33 tied to ground (GND). To avoid power-sequencing,
VRC33 must be powered up within the specified operating range, even if the on-chip voltage regulator
controller is not used. Refer to Section 3.7.2, “Power-Up Sequence (VRC33 Grounded),” and
Power sequencing requires that VDD33 must reach a certain voltage where the values are read as ones
before the POR signal negates. Refer to Section 3.7.1, “Input Value of Pins During POR Dependent on
Although power sequencing is not required between VRC33 and VDDSYN during power up, VRC33 must
not lead VDDSYN by more than 600 mV or lag by more than 100 mV for the VRC stage turn-on to operate
within specification. Higher spikes in the emitter current of the pass transistor occur if VRC33 leads or lags
VDDSYN by more than these amounts. The value of that higher spike in current depends on the board power
supply circuitry and the amount of board level capacitance.
8
Voltage differential during power up such that:
VDD33 can lag VDDSYN or VDDEH6 before VDDSYN and VDDEH6 reach the
VPOR33 and VPOR5 minimums respectively.
VDD33_LAG
—1.0
V
9
Absolute value of slew rate on power supply pins
—
50
V/ms
10
Required gain at Tj:
IDD IVRCCTL (@ fsys = fMAX)
BETA11
70
—
– 40o C70
—
——
150o C
10511
500
—
1 The internal POR signals are V
POR15, VPOR33, and VPOR5. On power up, assert RESET before the internal POR negates.
RESET must remain asserted until the power supplies are within the operating conditions as specified in Table 9 DC Electrical
Specifications. On power down, assert RESET before any power supplies fall outside the operating conditions and until the
internal POR asserts.
2 V
3 Supply full operating current for the 1.5 V supply when the 3.3 V supply reaches this range.
4 It is possible to reach the current limit during ramp up—do not treat this event as short circuit current.
5 At peak current for device.
6 Requires compliance with Freescale’s recommended board requirements and transistor recommendations. Board signal
traces/routing from the VRCCTL package signal to the base of the external pass transistor and between the emitter of the pass
transistor to the VDD package signals must have a maximum of 100 nH inductance and minimal resistance
(less than 1
). V
RCCTL must have a nominal 1 F phase compensation capacitor to ground. VDD must have a 20 F (nominal)
bulk capacitor (greater than 4
F over all conditions, including lifetime). Place high-frequency bypass capacitors consisting of
eight 0.01
F, two 0.1 F, and one 1 F capacitors around the package on the V
DD supply signals.
7 Only available on devices that support -55o C.
8 I
VRCCTL is measured at the following conditions: VDD = 1.35 V, VRC33 = 3.1 V, VVRCCTL = 2.2 V.
9 Refer to Table 1 for the maximum operating frequency.
10 Values are based on I
DD from high-use applications as explained in the IDD Electrical Specification.
11 BETA represents the worst-case external transistor. It is measured on a per-part basis and calculated as (I
DD IVRCCTL).
Table 6. VRC and POR Electrical Specifications (continued)
Spec
Characteristic
Symbol
Min.
Max.
Units
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