MOTOROLA
Chapter 3. Central Processing Unit
3-23
OEA Register Set
18
FP
Floating-point available.
0 The processor prevents dispatch of floating-point instructions, including floating-point loads,
stores and moves. Floating-point enabled program exceptions can still occur and the FPRs
can still be accessed.
1 The processor can execute floating-point instructions, and can take floating-point enabled
exception type program exceptions.
19
ME
Machine check enable.
0 Machine check exceptions are disabled.
1 Machine check exceptions are enabled.
20
FE0
21
SE
Single-step trace enable.
0 The processor executes instructions normally.
1 The processor generates a single-step trace exception when the next instruction executes
successfully. When this bit is set, the processor dispatches instructions in strict program
order. Successful execution means the instruction caused no other exception.
22
BE
Branch trace enable.
0 No trace exception occurs when a branch instruction is completed.
1 Trace exception occurs when a branch instruction is completed.
23
FE1
24
—
Reserved
25
IP
Exception prefix. The setting of this bit specifies the location of the exception vector table.
0 Exception vector table starts at the physical address 0x0000 0000.
1 Exception vector table starts at the physical address 0xFFF0 0000.
26
IR
Instruction relocation.
0 Instruction address translation is off; the BBC IMPU does not check for address permission
attributes.
1 Instruction address translation is on; the BBC IMPU checks for address permission attributes.
27
DR
Data relocation.
0 Data address translation is off; the L2U DMPU does not check for address permission
attributes.
1 Data address translation is on; the L2U DMPU checks for addressn permission attributes.
28
—
Reserved
29
DCMPEN Decompression On/Off. The reset value of this bit is (BBCMCR[EN_COMP] AND
BBCMCR[EXC_COMP]).
Note: This bit should not be set for the MPC561/MPC563.
0 The RCPU runs in normal operation mode.
1 The RCPU runs in compressed mode.
Note: MSR[DCMPEN] should not be changed by software by a direct MSR register write
(MTMSR instruction). It can be changed only by the RFI instruction or by an exception.
30
RI
Recoverable exception (for machine check and non-maskable breakpoint exceptions).
0 Machine state is not recoverable.
1 Machine state is recoverable.
31
LE
Little-endian mode. This mode is not supported on MPC561/MPC563. This bit should be cleared
to 0 at all times.
0 The processor operates in big-endian mode during normal processing.
1 The processor operates in little-endian mode during normal processing.
Table 3-11. Machine State Register Bit Descriptions (continued)
Bits
Name
Description