MOTOROLA
Chapter 8. Clocks and Power Control
8-37
Clocks Unit Programming Model
14
LOCSS
Loss of clock sticky. If, after negation of PORESET, the loss-of-clock circuit detects that the
oscillator or external clock source is not at a minimum frequency, the LOCSS bit is set.
LOCSS remains set until software clears it by writing a one to it. A write of zero has no effect
on this bit. The reset value is determined during hard reset. The STBUC bit will be set
provided the PLL lock condition is not met when HRESET is asserted, and cleared if the PLL
is locked when HRESET is asserted.
0 No loss of oscillator has been detected
1 Loss of oscillator has been detected
15
SPLS
System PLL lock status bit
0 SPLL is currently not locked
1 SPLL is currently locked
16
SPLSS
SPLL lock status sticky bit. An out-of-lock sets the SPLSS bit. The bit remains set until
software clears it by writing a one to it. A write of zero has no effect on this bit. The bit is
cleared at power-on reset. This bit is not affected due to a software initiated loss-of-lock (MF
change and entering deep-sleep or power-down mode). The SPLSS bit is not affected by
hard reset.
0 SPLL has remained in lock
1 SPLL has gone out of lock at least once (not due to software-initiated loss of lock)
17
TEXPS
Timer expired status bit. This bit controls whether the chip negates the TEXP pin in
deep-sleep mode, thus enabling external circuitry to switch off the VDD (power-down mode).
When LPM = 11, CSRC = 0, and TEXPS is high, the TEXP pin remains asserted. When LPM
= 11, CSRC = 0, and TEXPS is low, the TEXPS pin is negated.
To enable automatic wake-up TEXPS is asserted when one of the following occurs:
The PIT is expired
The real-time clock alarm is set
The time base clock alarm is set
The decrementer exception occurs
The bit remains set until software clears it by writing a one to it. A write of zero has no effect
on this bit. TEXPS is set by power-on or hard reset.
0 TEXP is negated in deep-sleep mode
1 TEXP pin remains asserted always
18
TEXP_INVP Timer Expired Pin Inversed Polarity – The TEX_INVP bit controls whether the polarity of the
TEXP pin will be active high (normal default) or active low.
0 The TEXP pin is active high
1 The TEXP pin is active low
19
TMIST
Timers interrupt status.TMIST is set when an interrupt from the RTC, PIT, TB or DEC occurs.
The TMIST bit is cleared by writing a one to it. Writing a zero has no effect on this bit. The
system clock frequency remains at its high frequency value (defined by DFNH) if the TMIST
bit is set, even if the CSRC bit in the PLPRCR is set (DFNL enabled) and conditions to switch
to normal-low mode do not exist. This bit is cleared during power-on or hard reset.
0 No timer expired event was detected
1 A timer expire event was detected
20
—
Reserved
21
CSRC
Clock source. This bit is cleared at hard reset.
0 General system clock is determined by the DFNH value
1 General system clock is determined by the DFNL value
Table 8-11. PLPRCR Bit Descriptions (continued)
Bits
Name
Description