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參數(shù)資料
| 型號： | MPC604E |
| 廠商： | Motorola, Inc. |
| 英文描述： | PowerPC 604e-TM RISC Microprocessor Technical Summary |
| 中文描述： | 的PowerPC 604e -商標(biāo)RISC微處理器技術(shù)總結(jié) |
| 文件頁數(shù)： | 2/34頁 |
| 文件大小： | 117K |
| 代理商： | MPC604E |
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PowerPC 604e RISC Microprocessor Technical Summary
Part 1 PowerPC 604e Microprocessor Overview
This section describes the features of the 604e, provides a block diagram showing the major functional units,
and describes briefly how those units interact.
The 604e is an implementation of the PowerPC family of reduced instruction set computer (RISC)
microprocessors. The 604e implements the PowerPC architecture as it is specified for 32-bit addressing,
which provides 32-bit effective (logical) addresses, integer data types of 8, 16, and 32 bits, and floating-
point data types of 32 and 64 bits (single-precision and double-precision). For 64-bit PowerPC
implementations, the PowerPC architecture provides additional 64-bit integer data types, 64-bit addressing,
and related features.
The 604e is a superscalar processor capable of issuing four instructions simultaneously. As many as seven
instructions can finish execution in parallel. The 604e has seven execution units that can operate in parallel:
Floating-point unit (FPU)
Branch processing unit (BPU)
Condition register unit (CRU)
Load/store unit (LSU)
Three integer units (IUs):
— Two single-cycle integer units (SCIUs)
— One multiple-cycle integer unit (MCIU)
This parallel design, combined with the PowerPC architecture’s specification of uniform instructions that
allows for rapid execution times, yields high efficiency and throughput. The 604e’s rename buffers,
reservation stations, dynamic branch prediction, and completion unit increase instruction throughput,
guarantee in-order completion, and ensure a precise exception model. (Note that the PowerPC architecture
specification refers to all exceptions as interrupts.)
The 604e has separate memory management units (MMUs) and separate 32-Kbyte on-chip caches for
instructions and data. The 604e implements two 128-entry, two-way set associative translation lookaside
buffers (TLBs), one for instructions and one for data, and provides support for demand-paged virtual
memory address translation and variable-sized block translation. The TLBs and the cache use least-recently
used (LRU) replacement algorithms.
The 604e has a 64-bit external data bus and a 32-bit address bus. The 604e interface protocol allows multiple
masters to compete for system resources through a central external arbiter. Additionally, on-chip snooping
logic maintains data cache coherency for multiprocessor applications. The 604e supports single-beat and
burst data transfers for memory accesses and memory-mapped I/O accesses.
The 604e uses an advanced, 2.5-V CMOS process technology and is fully compatible with TTL devices.
1.1 PowerPC 604e Microprocessor Features
This section summarizes features of the 604e’s implementation of the PowerPC architecture.
Figure 1 provides a block diagram showing features of the 604e. Note that this is a conceptual block
diagram intended to show the basic features rather than an attempt to show how these features are physically
implemented on the chip.
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